Adding simplicity, predictability, and flexibility to the physical implementation process.
By Terence Chen and Alexander Volkov
Power-sensitive ICs for wearables and internet of things (IoT) products are in demand for markets ranging from automotive to military/aerospace to consumer. As with most ICs, cost and time-to-market pressures are important determiners of success. Reducing risk by using a vendor-created reference flow can confer a serious business advantage.
Reference flows are popular because building a custom flow takes time and specialized knowledge, introduces risk, and increases both the total cost of tool ownership and time to tapeout. Reference flows for a specific technology are verified by both the EDA vendor and the fab, letting the designers focus on creating value instead of creating a design flow.
Mentor and UMC supply their customers with a complete reference flow for digital and mixed-signal design for the UMC 22uLP technology. The reference flow includes scripts that automate each step of the flow, a user guide, and design data for demonstration (Arm Cortex-M33 processor).
The UMC 22uLP process features a 10 percent area reduction, improved power-to-performance ratio, and enhanced RF capabilities compared to the company’s 28nm High-K/Metal gate process. The platform is ideal for a wide variety of applications and is well-suited for power-sensitive ICs that require long battery life.
At the heart of the Mentor/UMC reference flow is the knowledge-based set of recipes called the Nitro Reference Flow (NRF), which is included with Mentor’s Nitro- SoC digital implementation tool.
Physical implementation tools are notoriously complicated and hard to use. Even experienced design teams can waste valuable time just getting the tools set up, the environment tuned just right, and the command settings perfected for their design. This is the challenge Mentor’s Nitro-SoC team took: create a flow that gives fast results out of the box but allows for easy customization and tuning to create the most optimized results. The goal was to simplify the user experience and add predictability and flexibility to the physical implementation process. The result is the NRF.
The NRF enables rapid design bring-up and fast time to first results with minimal user effort, plus best-in-class low power optimization. The NRF directs all stages of the place-and-route flow from data preparation to post-route optimization, as shown in Figure 1. The NRF is proven in customers’ success tape-outs.
Figure 1: The Nitro Reference Flow provides full control of core implementation tasks, covering everything needed for a faster time to first results and a successful tapeout.
The NRF excels in ultra-low power implementation. Low power techniques include concurrent multi-Vt optimization, power gating, retention flop synthesis, and power-aware buffering and sizing. Power-aware CTS minimizes power in the clock network and ensures a balanced clock tree with optimal power. The tool supports the Unified Power Format (UPF), including the ability to describe design intent through power state definition tables.
The physical design reference flow starts with logic synthesis and proceeds through floorplanning, place and routing, and static timing analysis, and DRC/LVS signoff – all highly automated by the NRF for quick time to results. The full physical design flow is shown in Figure 2.
Figure 2: The full Arm Cortex-M33 processor flow presented in this blog.
The reference flow includes Tcl scripts for synthesis, optimization, design-for-test (DFT), and logic equivalence checking (LEC). The DFT and LEC steps are done through “under-the-hood” calls to Mentor’s FormalPro and Tessent tools.
For the place and route portion of the reference flow, the NRF calls on a fully customizable and configurable chain of core engines to give users full control with less effort. It is based on best practices from years of design closure knowledge to provide competitive quality of results right out of the box. The NRF is set up with one command: setup_nrf. The NRF scripts are shown in Figure 3.
Figure 3: NRF scripts.
In addition to the main scripts described above, there are three supporting Tcl files. One is called import_ variables.tcl and is used to specify the design libraries, technology file, parasitic extraction tech file, design modes and corners, and the use of a default or custom floorplan including the power/ground grid. The second file is called flow_variables.tcl. This file is used to describe the details of the flow, including:
The third supporting file is known as the NRF customization file and can be used for virtually unlimited customization of the flow. The NRF customization file has a section for each of the three implementation steps—placement, CTS, and routing. By adding custom Tcl to these sections, the flow can be customized to suit the design characteristics and goals.
There is one other mechanism for customization, called event handlers. Each section in the NRF customization file has a generic event handler that allows for the interruption of the flow at specific stages so that custom scripts can be executed before continuing with the flow. In addition, a finer-grained event handler can be inserted into the NRF customization file, which will cause custom Tcl to be executed after any Nitro-SoC command. By using the customization features of NRF, the flow can essentially become a custom flow using a generic infrastructure, which has the effect of lowering the cost of ownership associated with the implementation tool.
Users can run each script and review the results to ensure that everything is right. The scripts run automatically, with no need for users to interact with the process.
Static timing analysis in this reference flow is accomplished with a call to the Nitro-SoC built-in static timing analysis (STA), which uses the engines of Mentor’s Optimus-DS tool. Inputs include netlists, constraints, libraries, and LEF and DEF files. If the design requires optimizations to meet timing, that can be performed from within Nitro-SoC.
Nitro-SoC is natively integrated with the Calibre engines, and so the NRF includes calls to Calibre for DRC and LVS sign-off. Having a full router integrated with DRC signoff greatly reduces the physical verification ECOs and enables signoff checks during implementation.
The UMC 22uLP reference flow is demonstrated using an Arm Cortex-M33 processor. The Cortex-M processor series is designed to enable developers to create cost-sensitive and power-constrained solutions for a broad range of devices. Optimized for cost and power-sensitive microcontroller and mixed-signal applications, the Cortex-M33 processor is designed to address embedded and Internet of Things (IoT) markets, especially those that require efficient security or digital signal control.
The specification is below:
The implemented corners are the following:
Figure 4 shows the design after synthesis, DRC, LEC, and place & route with the Nitro reference flow.
Figure 4: Results of place and route with the NRF.
This full digital design reference flow comes with an automated and well-documented set of data and scripts to run synthesis, LEC, DFT, place & route with a low-power setup, DRC/LVS, and static timing analysis. Customers of Mentor and UMC can modify the scripts to complete any design with UMC technologies.
Reference flows are a result of tight collaboration between various semiconductor ecosystem vendors. They provide IC designers with a short-cut to success by reducing time-to-market, development costs, and risk.
Read more about the UMC 22uLP reference flow with Mentor in our whitepaper.
Alexander Volkov is P&R Technologist for the place and route group at Mentor, a Siemens Business.
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