Accelerated Optimization With IC Compiler II

Efficient optimization is a necessary, yet challenging aspect of the physical implementation flow. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges. Click here to read more. » read more

ECO Should Not Stand For Extended Challenge Order

There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such task. Ideally, when the design has been placed and routed (physical implementation), final analysis of timing and other metrics is performed and an engineering change order (ECO) file is issued to t... » read more

Optimizing For Energy In Physical Design

Energy is a precious resource, which should not be wasted. Energy drives economies and sustains societies. Predictions show that the energy of electronics may soon consume 20% to 33% of the global energy supply, as it is highlighted in this blog post about "Design and Manufacturing in 2030" from Greg Yeric, fellow at Arm. Energy efficiency is such an important global issue that it is ... » read more

Easier Low Power ICs With Reference Flows

By Terence Chen and Alexander Volkov Power-sensitive ICs for wearables and internet of things (IoT) products are in demand for markets ranging from automotive to military/aerospace to consumer. As with most ICs, cost and time-to-market pressures are important determiners of success. Reducing risk by using a vendor-created reference flow can confer a serious business advantage. Reference f... » read more