Top Stories
SoC Power Grid Challenges
How efficient is the power delivery network of an SoC, and how much are they overdesigning to avoid a multitude of problems?
Implementation Limits Power Optimization
Why dynamic power, static leakage and thermal issues need to be dealt with throughout the design process.
No More Easy IP Money
Revenues for semiconductor IP are expected to grow, but the easy money may have already been made. Developing IP is getting tougher on several fronts.
Mixed-Signal/Low-Power Design
Experts at the table, part 1: Adding ultra-low-power requirements to a device design is complicating the traditional process of mixed-signal IC design.
Blogs
Editor In Chief Ed Sperling observes that discussions are shifting to what can be done with technology, not how to improve it, in New Starting Point.
Executive Editor Ann Steffora Mutschler contends that getting power right makes the designer’s job much more interesting, in Power Confounds, Challenges.
Ansys’ Karthik Srinivasan points to a number of challenges facing the power management IC market and how to deal with them, in Better PMIC Design Using Multi-Physics Simulation.
Cadence’s Christine Young examines advances in brain/machine interfaces and new ways to look inside the brain, in Designing Power-Efficient, Implantable Medical Devices.
Mentor Graphics’ Ahmed Eisawy and On Semi’s Andrew Talan dig into verifying chips that must survive harsh environments, in Addressing The Challenges Of Automotive Motor Control.
ARM’s Brian Fuller argues that as IoT becomes more successful, hacking it will become increasingly attractive, in How To Scale IoT For “Time To Money,” Security.
Synopsys’ Eric Huang sheds some light on which flavor of USB should be used when designing an IoT SoC, in The Indisputable Case For USB 2.0 Type-C In IoT Applications.
Independent power architect Barry Pangrle zeroes in on the Olympics of supercomputers, in China Tops Top500.
