Better PMIC Design Using Multi-Physics Simulation

Challenges facing the power management IC market and how to deal with them.


Energy efficiency and thermal management are gaining importance in the IC and system design community.

Because the integrated circuit is the major source of power consumption and hence heat dissipation, semiconductor companies are under immense pressure to reduce the overall power envelope of the IC that goes into the system. This phenomenon is seen globally, irrespective of whether the chip is a microprocessor in the laptops, applications/baseband processors in smartphones or a networking chip used in data centers or base stations. Although the scale of power consumption is different, the goal of achieving energy efficiency is common among a broad spectrum of applications. With the advent of the Internet of Things (IoT), one can expect billions of devices communicating with each other and many are expected to work on coin-cell or thinner batteries in harsh environments for years without any significant maintenance overhead. This is a new class of application that pushes the need of power and energy efficiencies to its extreme levels.

The semiconductor industry has made significant progress in achieving higher levels of integration within a smaller footprint and higher performance. But such high levels of integration not only mean better throughput, it also means higher power density. Several advanced power optimization techniques like multiple power islands, clock/power gating, back-biasing, near threshold computing, etc. have been used by the industry over the years to reduce idle and active power consumption of the chip. Such techniques do help in reducing the power consumption, but puts added overhead on a cleaner power supply and hence better power management techniques.

A typical SoC may have several tens of power supplies with voltage levels ranging all the way from 0.6 to 3.3V or even higher. While integrating the SoC in a system, it may require one or many regulator modules supplying these different voltages at required load current levels. Power Management ICs (PMIC) provide an efficient way of supplying the required power to different SoCs in the system. With such diverse applications, the PMIC market is a rapidly growing with CAGR ~6.1% and is projected to reach ~$49 billion by 2019.

A typical PMIC contains single or multiple switching DC-to-DC converters like buck or boost converters and linear regulators like Low-Drop Out (LDO). At the heart of a PMIC is the power-transistor, which is a large transistor with an area of a few square millimeters laid out as multiple banks of transistors. It is critical for these parallel devices to have very low resistance (aka RdsON) in order to minimize the power loss, heat, and achieve better power conversion efficiency.

Although PMICs are still done in older process nodes, these buck converters are switching at the few MHz range, so the designers can use smaller off-chip inductors. For better and smoother integration, PMICs continue to shift from analog-heavy implementations to using digital techniques. The PMICs are becoming highly integrated and multi-functional designs and include blocks like ADC, timers, audio, USB and touch screen functionalities.

There are few major challenges to the designers of PMICs:

  1. Reduction in the cost and area/size of the IC so that is ideal for portable applications.
  2. Reducing the thermal dissipation and improved reliability/lifetime.
  3. Noise coupling between power FET devices to other sensitive devices in the chip through power/ground and substrate networks.
  4. Improved ESD/Latch-up robustness and minimizing the near-field EMI radiation from switching regulators.
  5. Other new technologies like wireless charging impose new challenges like interference.

To address the above challenges and to optimize the design cycle, a simulation-driven verification approach is necessary. Currently PMIC designers use the design expertise, layout guidelines and some tools to verify the Rds-ON of power devices. Such checks are often done after the initial layout, so designers have some flexibility in modifying the layouts. In-design, simulation-based feedback is extremely critical for designers to make major design decisions early in the design cycle which may reduce the overall design cycle and cost. Simulation platforms should be able to address multi-physics problems like power/thermal, substrate noise coupling, ESD/EMI, etc., and the ability to handle highly integrated and complex multi-function PMICs.

Register for the ANSYS webinar on Designing Reliable Power Management ICs: Tips and Tricks.


Akarsh says:

Hello Karthik,

Thanks for the article. I’m in search of how to calculate power loss of each DCDC switching converters in a PMIC. In fact there is no rds on or any switching or conduction loss is mentioned in the datasheet. Could you help me with normal procedures ?

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