Special Report
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
Top Stories
Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
Gates Add Functionality, But Wires Create Problems
Wires are treated as a lesser concern, but their neglect is becoming critical at advanced nodes.
Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Video
New CPU Memory Module
Benefits and questions surrounding a next-gen low-power standard for high-performance compute.
Why More CPUs Are Needed For Agentic AI
General-purpose processing demands will multiply once machines are talking to machines.
Sponsor Blogs
Expedera’s Athish Rahul Rao explains why peak TOPS is becoming a weaker proxy for actual edge performance, in Why Vision LLMs Force A Rethink Of Edge AI Hardware.
Rambus’ Piero Bianco digs into preserving LPDDR’s energy efficiency advantages while restoring the modularity required for server systems, in SOCAMM2: Bringing LPDDR5X Benefits To AI Servers.
Quadric’s Mike Leonard details an emerging AI architecture for embedded autonomy that improves edge efficiency, in Vision-Language-Action Models Arrive.
Arm’s Jade Alglave introduces an experimental AI chatbot that acts as a guide to the Arm architecture, providing quick answers to complex technical questions, in Introducing “The Architecture Speaks.”
Cadence’s Veena Parthan compares the accuracy of two meshing workflows when dealing with complex blade geometries, in Structured Or Unstructured Meshes: What Works Best For Turbomachinery CFD.
Siemens EDA’s Carey Robertson explains how AI can speed sign-off while increasing confidence that a design will function as expected, in Harnessing Artificial Intelligence For Trusted IC Signoff.
Sponsor White Papers
ASIC Prototyping — New Design Realities Demand A New Approach
Why at-speed prototyping is necessary to deal with rising design complexity, and to maintain verification agility and coverage.
Scaling PCIe Controllers for AI Bandwidth: A Multistream Architecture Analysis for 64 GT/s and 128 GT/s
As PCIe moves toward 128 GT/s and beyond, multistream architecture transitions from an optimization to a requirement.
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