Top Stories
Processor Tradeoffs For AI Workloads
Gaps are widening between technology advances and demands, and closing them is becoming more difficult.
Specialization Vs. Generalization In Processors
What will it take to achieve mass customization at the edge, with high performance and low power?
MRAM Getting More Attention At Smallest Nodes
Why this 25-year-old technology may be the memory of choice for leading-edge designs and in automotive applications.
Blogs
Fraunhofer IIS/EAS’ Ron Martin and Christoph Sohrmann advise coupling computing hardware models with sensor models for better simulation of automated driving functions, in Virtual Development Of Perception Sensor Systems.
Rambus’ Lou Ternullo digs into PAM4 signaling, which offers much higher data rates as well as new challenges for PCB and package design, in Using A Retimer To Extend Reach For PCIe 6.0 Designs.
Synopsys’ William Ruby explains how end-to-end power analysis helps achieve optimal performance-per-watt, in Developing Energy-Efficient AI Accelerators For Intelligent Edge Computing And Data Centers.
Quadric’s Steve Roddy looks at graph compilers, which are just getting started, in Compiler-Driven Performance Boosts For GPNPUs.
Ansys’ Akanksha Soni gives a fresh introduction to the chip industry and where it’s headed with 2.5D and 3D-IC, in What Is An Integrated Circuit?
Siemens’ Jimmy Tien explains why an automated via kit migration is needed to support new technology nodes and rule decks, in Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance.
Arm’s Jamie Cunliffe offers key tips for porting Neon code to Rust and differences from C, in Neon Intrinsics In Rust.
Cadence’s Veena Parthan shows how to avoid cavities, overlapping surfaces, extrusions, and saddle corners that impede quality meshing, in Cleaning Marine Geometries Has Never Been Easier.
Sponsor White Papers
Achieving High-Performance, Low-Power Design Optimization With The Solido Library IP Solution
Verifying library IP to optimize power, performance and area tradeoffs.
Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces
The interplay of clock and data paths, and how to understand and manage jitter effectively.
Arm Total Compute: Engineering For Tomorrow’s Workloads
An approach to system-on-chip design that moves beyond individual IP elements to design and optimize the system as a whole.
Ansys Charge Plus And Its Particle-In-Cell Solver
A tool uniquely suited to modeling and simulating charged plasmas and their sudden discharges with industry-leading accuracy.
New Research eBook
Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
Chiplets may be the semiconductor industry’s hardest challenge yet, but they are the best path forward.
Newsletter Signup
Find our email newsletter signup page here.
