Special Report
Impact Of GAA Transistors At 3/2nm
Some things will get better from a design perspective, while others will be worse.
Top Stories
Lowering Energy Per Bit
Why reining in energy requires changes across the entire semiconductor ecosystem.
Adding Aging To Variability
Traditionally these effects were analyzed separately, but they’re now heavily intertwined.
The Search For 5G MmWave Filters
New options abound, but so far there’s no clear winner.
Blogs
Arm’s John Bigg names the missing component needed for a complete flexible integrated smart system, in The “Natively Flexible” Processor Has Arrived: Here’s What We Need To Make It Mainstream.
Siemens EDA’s Dina Medhat looks at using topology-aware and voltage-aware flows to address external and mixed-voltage latch-up design rules, in Now You Can Automate Latch-Up Verification For 2.5/3D Technologies.
Synopsys’ Anand Thiruvengadam contends that changes are needed to improve the reliability of memories and shorten the design time, in Time To Rethink Memory Chip Design And Verification.
Fraunhofer IIS EAS’ Jens Michael Warmuth examines how standards help spread safety processes throughout the supply chain, in Functional Safety: Current Status And Perspectives With A View Toward Standardization Bodies.
Ansys’ Nikhil Grover lays out ways to avoid electromagnetic interference issues in PCB routing, in PCB Design Rules For Wiring And Crosstalk.
Rambus’ Frank Ferro shows how ultra-low latency and AI/ML inferencing team up to power cloud gaming and other new applications, in GDDR6 Memory On The Leading Edge.
Cadence’s John Chawner develops skills that aren’t always taught in the classroom, in What Is Intern Reading Club?
White Papers
Servers And The Drive To DDR5
Condition Monitoring Of Drive Trains By Data Fusion Of Acoustic Emission And Vibration Sensors
Physics-Based Sensor Validation Via Ansys: Driving New Automotive Innovations
2.5D And 3D-IC Latch-Up Prevention
Radar Wave Propagation Through Materials
Post-Quantum Cryptography
10X Higher Productivity With VCS Dynamic Test Loading
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