Special Report
Foundational Changes In Chip Architectures
New memory approaches and challenges in scaling CMOS point to radical changes — and potentially huge improvements — in semiconductor designs.
Top Stories
Designing A Better Clock Network
Optimal power, performance, and timing hinge on making the right decisions about the clock network architecture.
Dealing With Heat In Near-Memory Compute Architectures
Shortening data paths between processor and memory may help, but not always.
Complex Tradeoffs In Inferencing Chips
One size does not fit all, and each processor type has its own benefits and drawbacks.
Video
HBM3 In The Data Center
What the new version of high-bandwidth memory will bring, and where the challenges are.
Blogs
Cadence’s Tom Beckley examines what is needed to succeed with system-in-package, in Heterogeneous Integration Co-Design Won’t Be Easy.
Synopsys’ Manoz Palaparthi shows how to ferret out the root causes of early full-chip LVS faster, in Meeting Today’s Challenges For LVS.
Siemens’ Janet Attar presents a case study in low-power and high-performance AI processors, in Designing Edge AI Chips Small And Cool.
Arm’s Jack Melling looks at how a lack of hardware and firmware standardization between SoCs can hinder the deployment of edge computing applications, in The New Disruptive Force In High-End AIoT Markets.
Ansys’ Kelly Damalou and Pete Gasperini examines how to deal with unexpected challenges in advanced packaging, in What’s So Different About Interposer Signal Integrity?
White Papers
Best Practice: Scale-Resolving Simulations In Ansys CFD
A general understanding of the underlying principles and the associated limitations of the described modeling concepts.
Silicon Lifecycle Management Platform
Optimizing each stage of the silicon lifecycle from design to in-field.
Detection Of Electric Vehicles And Photovoltaic Systems In Smart Meter Data
An approach to identify energy sources and sinks as soon as new devices are installed to ensure grid stability.
PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangemen
A programmable near-memory accelerator that rearranges sparse data into dense. The device leads to significant reductions in data movement and dynamic energy.
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