Heterogeneous Integration Co-Design Won’t Be Easy

What’s needed to succeed with system-in-package.


The days of “throwing it over the wall” are over. Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core—one that lives or dies on seamless interaction between your analog and digital IC and package design teams.

Heterogeneous integration is the use of advanced packaging technologies to combine smaller, discrete chiplets into one system-in-package (SiP). It not only pushes the need for more advanced multi-die packaging, it makes it part and parcel of the process. And in doing so, it significantly reduces dependence on Moore’s Law at a time when building an advanced monolithic system on chip (SoC) has become highly complex, and prohibitively expensive for all but very high volume devices.

Practically every day, I encounter companies for which Moore’s Law no longer represents the best technical or economical path to designing a silicon chip. And for a great many of those companies, heterogeneous integration presents a high-performance solution—SiPs close to the SoC form factor but with far lower overall cost, greater yield, and perhaps most importantly, faster time to market. While SiP as a packaging concept has been around for decades, the recent tsunami of designs adopting heterogeneous integration is truly a disruptive change.

Moore himself knew this day might come. Page 3 of his seminal 1962 Electronics paper admits, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”

The industry is rapidly waking up, too. Pat Gelsinger’s affirmation earlier this year that Intel’s foundry business would embrace heterogeneous integration in combining x86, Arm, or RISC-V chiplets put to rest my biggest fear—that heterogeneous integration would remain, as it had been until then, a closed ecosystem forged by vertically integrated companies designing chiplets and interconnects for their own use and advantage.

Heterogeneous integration: Collaboration is crucial

There is, however, a caveat and it’s a big one. Implementing and verifying heterogeneous integration designs with multiple chiplets is inherently more difficult than designing an SoC. Managing longer signal paths (though this can be mitigated with 3D integration), more I/Os, and a larger form factor will disappoint chip designers accustomed to SoC levels of optimization in power, performance, and area (PPA).

Instead, they’ll have a whole new list of design tradeoffs to overcome. Moving from a single monolithic SoC to a system in package (SiP) architecture requires continuous analysis of electrical, thermal, and mechanical interactions among chiplets, the substrate, and the package.

It’s therefore imperative that engineering teams looking at heterogeneous integration are capable of seamless co-design, capturing and sharing design complexities between various entities using EDA tools and flows built from the ground up to enable truly cross-functional co-analysis and co-optimization.

I’m talking about complete system-level visualization in a single tool, with the ability to optimize system-level designs and cross-domain interconnects, pin-out and floorplans (including stack), and direct read/write capability into multiple layout domains and tools.

If the chip, package, and board are not designed cooperatively and as a system, performance will be reduced, additional board layers may be needed, and board and package costs may rise significantly. And without co-design, timing, power, and signal integrity will not be optimized.

Simulation will also become highly important to understand how the electrothermal and thermo-mechanical elements of a design will perform at an early stage. Consider, for example, that with heterogeneous integration, the base die itself could become the key path to the heatsink in the final package and PCB. That’s great for anything attached to it, but what about 3D stacking of dies above the base die?

3D-IC architectures typically require substrate thinning, resulting in relatively poor heat dissipation across the 3D stack and making accurate thermal simulation and signoff a critical step in the design flow. How might best can designers transfer heat away from each of the chiplets and overall package?

The complete package

It’s this kind of consideration that demonstrates just how integral your choice of packaging, and its implementation, will be in successfully creating a design based on heterogeneous integration.

Gone are the days of countless workhours spent reaching tapeout before any thought is put into how the chip will be packaged. As AMD CEO Lisa Su reminded audiences at Computex last year, a chip’s packaging is just as important as the chip design and chip process. To succeed, all three must be optimized together.

And exactly how we package heterogeneous integration is currently the name of the game. I’m seeing customers exploring everything from traditional SiP and MCM to fan-out wafer level packaging (FOWLP), bumpless 3D integration, 3D system-on-a-wafer, and even cutting-edge co-packaged optics.

It helps that we finally have a standard die-to-die (D2D) interconnect standard. Universal Chiplet Interconnect Express (UCIe) is the standard chiplet-to-chiplet interface, defined by a consortium of industry heavyweights including AMD, Arm, Intel, Microsoft, and Cadence. The UCIe 1.0 specification was released in March 2022 and encompasses a physical layer, protocol stack, software model, and compliance testing. This takes us a step closer to bringing different chiplets from different providers closer together in pursuit of the lower latency, greater flexibility, enhanced performance, and improved functional density.

The right tool(s) for the job

The transition to a heterogeneous integration chiplet-based approach introduces new EDA tool and solution challenges for chip designers and package designers. Designing something as complex as a cutting-edge, heterogeneously integrated SiP requires cross-domain design flows that enable users to seamlessly plan, design, analyze, and verify across chiplet, interposer, package substrate, and board.

This starts with a logical and hierarchical representation of the complete SiP, from the transistor level through the full system-level design.

Cadence has a broad set of advanced IC packaging solutions, from IC and package design to IC verification and system-level analysis. So, while heterogeneous integration won’t be easy, your design teams will find everything they need for successful co-design, co-optimization, and co-analysis of heterogeneous integration-based systems.

Read More: Heterogeneous Integration vs System on Chip: What’s the Difference?

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