Top Stories
Revving Up SiC And GaN
These technologies are gaining traction in high-voltage applications, but economies of scale and predictability still haven’t fully kicked in.
Amdahl Limits On AI
The application of old techniques to new problems only gets you so far. To remove limitations in AI processors, new thinking is required.
Can Coherent Optics Reduce Data-Center Power?
The good and bad of replacing electrical signals with optical ones.
Innovations In Sensor Technology
Better management of data, increased accuracy, and lower power approaches top the list.
Improving Energy And Power Efficiency In The Data Center
Optimizing energy and power efficiency in server chips and software is a multifaceted challenge with many moving parts.
Batteries Take Center Stage
No matter how efficient a system design, it only works when there is enough battery power.
Tech Talk
Always-On DSPs
The best ways to deploy digital signal processors and why multiple DSPs are better than one.
Blogs
Fraunhofer’s Christian Skubich and Nico Peter discuss challenges and benefits of applying Agile methods to hardware development, in Continuous Integration For Digital Design.
Rambus’ John Eble foresees a 50% increase in data rates for server memory, in Scaling DDR5 RDIMMs To 5600 MT/S.
Ansys’ Kara Gremillion explains why roles, capabilities, and limitations are essential to finding the right combination of sensors, in Choose The Right Sensors For Autonomous Vehicles.
Arm’s Parag Beeraka shows how to enable local execution of inferencing tasks on streams of incoming video, in The Future Of Smart Cameras Is 64-Bit Processing.
Cadence’s Min Lei zeroes in on faster and more efficient interconnects, in Moving From AMBA ACE To CHI For Coherency.
Synopsys’ Godwin Maben digs into how to understand power consumption in the real world, in Run Realistic Software For Full Chip Power Signoff.
Siemens EDA’s Srinivas Velivala examines how to reduce potential correlation issues between the P&R fill and the signoff fill, in Shifting Left In P&R With In-Design Signoff Fill For Faster And More Accurate Tapeouts.
Sponsor White Papers
The Physics Of Ports And Associated Ground For EM Simulators Serving RF Designs
Understand the ports common to EM simulators, which are the most common simulators for microwave and RF designs at the board, package, and chip level.
How Safety Requirements For Autonomous Vehicles Will Reinvent Fuse And Relay Boxes In Automotive Power Distribution
The automotive industry, and consumers, not only benefit from associated weight savings in the cable loom and improved failure analysis.
Veloce Prototyping Solutions Accelerate Verification Of HPC AI-Enabled SoCs
Step-by-step in-circuit emulation, from block to full-system.
Simulation Workflow For Efficiency Calculation Of A High-Performance Electric Powertrain
This workflow was developed as part of the partnership between Ansys and the TAG Heuer Porsche Formula E Team to maximize powertrain efficiency of Porsche´s first fully electric race car — the Porsche 99X Electric.
Design Meets EDA: Gaps And Countermeasures In Analog/Mixed-Signal IC Design
Systematic alternative approaches to designing analog/mixed-signal chips comprising EDA, tools, tool interfaces, and usability aspects.
Arm Neoverse N1 Core: Performance Analysis Methodology
Performance analysis on Neoverse N1 core using hardware PMU events.
Scaling Processor Performance And Safety To Meet Requirements For Next-Generation Safety-Critical Automotive Designs
A state-of-the-art processor architecture targeting automotive safety systems that meets the requirements of active safety systems delivering the required processing performance at the highest automotive safety integrity level (ASIL).
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