Moving From AMBA ACE to CHI For Coherency

Constructing interconnects that are more efficient and can run at higher clock frequencies.


Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in smart phones, mobile computers, and servers. It added new channels for cache communication, extra signals to allow new transaction for coherency support, and five state model for caches.

AXI + ACE Signals:

ACE was designed as an extension to AXI to handle coherency, but it is not without shortfalls. It served designs with smaller coherent clusters well, but as SoCs and systems became more complex and the number of processors increased, the need for better coherency and efficiency increased.

Enter CHI, Arm’s AMBA Coherent Hub Interface. In 2014, Arm released a fresh packet-based layered coherency architecture, without the dependencies on existing AXI or ACE. CHI was built with performance improvement and scalability in mind for applications and systems such as mobile, networking, automotive, and data center.

CHI addresses some of ACE’s deficiencies with:

  • Comprehensive layered (Protocol, Network, Link) functionality scalable from small to large systems
  • Four unified channels (REQ, SNP, DAT, RSP) reduce the number of wires
  • Link credits instead of valid and ready handshake streamlines transmission flow
  • Protocol centric flow control such as per channel link credits and RetryAck prevent blocking
  • More sophisticated cache state scheme enables timely response from caches
  • Cache stashing and atomic operations for data control

Arm once said, “Two factors that contribute to improving interface performance are a higher clock speed handshake and a clean separation of the information required for transport and the payload. This simplifies the interconnect transport task of shipping payload from one port of the interconnect to another. With these advances in CHI, interconnects can be constructed that are more efficient and can run at higher clock frequencies.”

“CHI ensures that the interconnect never becomes the bottleneck in the system.”

With the advances in CHI, has ACE been abandoned?

Even though CHI has industrial wide adoption, Arm continues to update ACE and include new features (atomic transactions, cache stashing, and Memory Tagging, to name a few) in the form of ACE5 and ACE5-lite. ACE continues to live on in IO coherent devices and legacy designs.

Jump over to Dimitry’s blog for a quick review of the latest AMBA 5 updates: What Is New in the Latest AMBA 5 ACE, AXI and AHB Protocol Specification Updates?

Since its initial release (CHI-A), and the first official release (CHI-B), Arm has revised and added to the CHI specification. Today, the latest update is CHI-E. In our next segment we will tackle the significance of each spec update.


Zhengji Lu says:

Nice article for ACE and CHI introduction.

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