Special Report
Issues And Options At 5nm
Lithographers look at the possibilities and challenges three nodes ahead and whether those are even the best options.
Top Stories
Searching For 3D Metrology
Techniques are evolving using multiple existing tools, with more technologies in research, but the ultimate solution may be a hybrid approach.
5 Reasons EUV Will Or Won’t Be Used
Opinions about EUV abound following each new announcement — good or bad—but what is required to get a data-driven assessment of the technology status?
3D Effects At 20nm And Beyond
Topography as a result of attenuated phase shift masks at 20nm and below requires taking 3D effects into account.
Challenges Mount For Patterning And Masks
Experts at the table, part 1: How much it will cost to develop chips at 7nm and 5nm; the current state of EUV; photomask issues.
ATE: The Road Ahead
SoC could down this year, but for memory it’s just getting started.
Blogs
Editor in Chief Ed Sperling looks at the increasing uncertainty in getting chips manufactured, what’s causing it and why it could reshape the entire chip industry, in Fab Capacity Shortages.
Executive Editor Mark LaPedus finds important issues that received very little attention at SPIE, in 5 Issues Under The SPIE Radar.
Mentor Graphics’ Jeff Wilson notes that because foundries are favoring established nodes instead of the leading edge processes, companies will need a deeper understanding of their DFM options, in Capacity Constraints And DFM At Mature Nodes.
Semico Research’s Joanne Itow travels to Semicon China to find traffic buzzing over $19B in government funding, the IoT, virtual reality and the JCET/STATS merger, in Full Steam Ahead For China Inc.
SEMI’s Bettina Weiss looks at the Indian government’s vision and the reality for three new fabs, in “Make In India.”
White Paper
Migrating Consumer Electronics To The Automotive Market With Calibre PERC
Many of the performance requirements for safety systems apply to IP used in systems that are not tied to safety, as well.
