Challenges Mount For Patterning And Masks

Experts at the table, part 1: How much it will cost to develop chips at 7nm and 5nm; the current state of EUV; photomask issues.


Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at Applied Materials; Pawitter Mangat, senior manager and deputy director for EUV lithography at GlobalFoundries; Aki Fujimura, chief executive at D2S; Naoya Hayashi, a fellow at Dai Nippon Printing (DNP); and Mike Rieger, senior director of engineering at Synopsys. What follows are excerpts of that discussion.

SE: From your vantage point, what are the big challenges in lithography today? And what do those challenges mean for ?

Fujimura: Cost is one issue. But we’ve also proven over the years that magically, somehow and some way, the collection of the SPIE community comes up with answers. It’s an amazing thing. I don’t think that it’s going to stop. Technology-wise, we will find answers. But it’s a question of funding. How much money will it take? Plus, it’s not true anymore that you get better performance at the next node and at the same price. Maybe it’s twice the performance at 60% of the increasing cost. The cost is increasing everywhere. That’s propagating everywhere and all the way through the supply chain. I don’t know if we can stop this as a trend. But at one node at a time, we need to come up with an innovation. We need to keep that going and that’s the challenge.

Rieger: Lithography, for a long time, has been the gaining factor in scaling. With scaling, you have all kinds of side benefits. You have a faster part at lower power. You have a lower cost and a smaller form factor. So all of these things were leveraged off of geometric dimensional scaling. But now there are other things coming up and a lot of these benefits are falling off. Clock speeds went away years ago. Power density is going up. Some people say that the cost is going up, but others say the cost is going down. Both people are right. From a transistor point of view, the cost is probably going down. But from a system point of view, there is so much excess stuff, such as buffers, repeaters and others. So the cost per system function is not going down as much, or maybe going up. The question is how do you continue the momentum?

Mitra: It’s not just lithography. I would rather use the word patterning in a broader context. Right now, we are focused on logic. But if you are in the NAND space, suppliers have used pitch division for five generations. And NAND is actually even more sensitive to cost. There are, of course, some big differences in terms of how you do logic. The layouts are very different. So suddenly cost is a challenge, along with edge placement error. That’s a big fundamental challenge. On the other side, you have a lot of innovation. Patterning is not just lithography, but you have a lot of precision materials engineering. You use 15 different types of films for hard masks, spacers and mandrels. And how you deposit, etch and control them very precisely is the key.

Mangat: We all talk about yield, power and cost. But one of the things we have to put into this picture is the business case for products that really need high-end 7nm to 5nm technology. For example, there’s STT MRAM. They are still doing 40nm. That’s a different type of memory, but there are opportunities for those types of things. But coming to the point, you have to look at cost from a business perspective. You also need a holistic approach. You can no longer say this is my EDA vendor, and this is my designer, and this is my mask shop. Actually, they are all in one box. They have to work together and come up with a solution, whether it’s in etch, materials, process enhancement or mask making. Mask making, for one, has taken the most beating. In the last four generations, we have been at 193nm immersion. What has changed? The mask.

Hayashi: From the mask side, people have been using 193nm immersion for a long time, so the minimum pitch size has not changed. But the cost pressure is quite high. And also, people sometimes want to change the material on the mask to enhance the process window. So we have to develop a new etching, repair or cleaning system. Also, some will use multi-patterning. So the mask-set has a large number of masks. They require a strict overlay. And that will impact yield. There is also cost pressure there. In addition, it’s quite difficult from a business point of view, especially in Japan. There are a small number of players or mask users. So the market size for a merchant mask shop has been squeezed.

SE: Any other issues?

Mangat: Specific to EUV, 2014 was a very positive year. We had a lot of good progress. On my own radar screen, we now see an 80 Watt EUV source. It’s not just one tool. There are other tools that are operating at 80 Watts. But I don’t think we can say: ‘Let’s celebrate.’ We can celebrate that we have a start. But these things were supposed to be done on the (ASML’s) NXE:3100. Now, we are on the new generation tool, the NXE:3300. And the next-generation NXE:3350 might take us to the next level. But we have a lot of challenges, such as the resists. Now, we have good news that there is no outgassing spec on the resist anymore. I’ve heard that ASML will supply the pellicles for customers. But at the end of the day, it’s the cost, and operating cost, of EUV. It’s one scanner versus five scanners. It’s the facilities. But from the capability side, we can get to single-level patterning. But that is also getting challenging.

Hayashi: For EUV we need an EUV-specific infrastructure, such as actinic inspection. But there is not enough investment to develop those kinds of things. So that’s a problem in the mask world.

Mangat: In addition, let’s do the mask blank supply calculation for EUV with the present infrastructure. If EUV goes into high-volume manufacturing in the next two years, people might have to bid on a good mask blank and say, ‘I am willing to pay so many thousands of dollars for it.’ There are only one or two suppliers for it. There might be only a limited number of volumes for blanks with high-quality yields.

Hayashi: Plus, even if the blank supplier could improve their process, they still cannot see the defects.

SE: The industry hopes EUV will be ready in time for 7nm. But to hedge their bets, the scanner suppliers are developing 193nm immersion lithography tools for 7nm and even 5nm. Will optical lithography with multi-patterning work at 7nm and 5nm if the industry needs it?

Fujimura: It’s just a question of cost. Technically, it’s feasible to do it. The high-volume manufacturers will probably do it. At BACUS, IBM said that we are all hoping that EUV is going to happen at 7nm. The leading-edge semiconductor business is going to be very different if we have to stick with 193nm immersion. It may limit the availability of the leading-edge nodes to a select few. High volumes may not be good enough anymore. You will need extremely high volumes.

Rieger: As optical lithography has become stressed, the materials aspect has really taken over. So at these smaller dimensions, we really owe it to the materials. People have talked about getting to a 24nm pitch at 5nm. From a materials point of view, you can probably make things that small, but there’s a lot of questions surrounding that, such as can you get to the required overlay. And then if you go back to the electrical side of things, there are a series of problems. For example, the resistance of interconnects is just skyrocketing. So does it make sense to have a 12nm wire if you can’t push any electrons through it? Also, on the design side, we are seeing a lot of changes in logic architecture and power management. Even the software is going to have to become much more power efficient. So it goes back to this question: How do we migrate all of the technologies so that there is a reason for people to get to the next node?

Mitra: Patterning is really evolving into two parts. First, there is the line and space. For line/space, 193nm is probably going to be used for a while, just to do the pitch division. Take a 14nm fin for example. It will be done with pitch division. Even if you look at 7nm, the fin pitch will be something like 20nm, 21nm or 24nm. You would use pitch division, probably with 193i. Now, that’s for the gratings with line and space. The grating part is actually not that difficult. The flash guys have put planar NAND in high production using SAQP or multiple patterning for many years now. The tricky part is cutting. How do you do all of the cuts? And do you do all the cuts simultaneously? You can’t use 193nm beyond a certain point. The question is how do you solve your edge placement and overlay problems. With 193nm, you can’t do all three or four cuts simultaneously. EUV can do that, at least maybe for the 7nm node, along with some tricks. Beyond that, at 5nm, even EUV at 0.33 NA can’t do it. So then you have to do something else. So, to answer the question, 193i for the line and space will probably be used for a long time, just to do the pitch division. Then, you need EUV or some other technology to do the cuts, and also for the holes and vias.

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