Top Stories
Etching Technology Advances
Atomic layer etch (ALE) moves to the forefront of chip-making technology—finally.
Inside Advanced Patterning
What’s in store for chipmakers at 7nm, 5nm and beyond, and why atomic-level etch and deposition are getting new attention.
BEOL Issues At 10nm And 7nm
Lines blur with middle of line as RC delay increases, reliability and yield become more difficult to achieve, and costs skyrocket.
Fab Tool Biz Faces Challenges In 2017
Outlook strong for some sectors, tepid for others. Consolidation, rising costs of development could take a toll.
Video
Tech Talk: FD-SOI vs. FinFET
Cost, performance, multi-patterning and the 12nm roadmap.
Blogs
Editor In Chief Ed Sperling argues that it’s time for the semiconductor industry to establish a new set of definitions, in Morphing Moore’s Law.
Executive Editor Mark LaPedus examines the buzz around next-generation technologies and issues, in 5 Takeaways From IEDM.
Mentor Graphics’ Elven Huang points to a better way to find and debug memory issues in finFET designs, in Using Automated Pattern Matching For SRAM Physical Verification.
National Instruments’ David Vye digs into why measurement is required to validate assumptions prior to fabrication, in Software Platforms Bridge The Design/Verification Gap For 5G Communications Design.
UMC’s Steve Sharp explains why a long history and continued improvements are keeping 40nm processes relevant, in 40nm Technology Reinvigorated.
Coventor’s David Fried looks at the top back end of line issues by way of an IEDM panel discussion, in BEOL Barricades Ahead.
