Morphing Moore’s Law

Shrinking features will continue, but it’s time to establish a new set of definitions.


In 1965, Gordon Moore defined a timetable for doubling the number of transistors on a piece of silicon every two years. The law, as he originally defined it, is now hopelessly outdated. Any attempts to apply it to the most advanced chips today are a stretch at best, and complete fiction at worst.

No one is on a two-year cadence between process nodes anymore—not even Intel. In fact, no one is even sure what numbers to use. Is a process node based on line width? Should the measurement be based on front-end of line or back-end of line? Ever since 20nm, those definitions have been getting fuzzy. Intel will have 7nm finFETs and 7nm back end of line, while pure-play foundries will have 7nm finFETs with a 10nm BEOL. Or it might be 8nm or 11nm, but who’s going to really challenge it?

One of the culprits behind this confusion is optical lithography and the wavelength of the laser used to pattern masks. EUV has a 13.5nm wavelength, so it can pattern metal 1 and metal 2 at the 14nm node with a single pass. 193nm immersion, in contrast, requires double patterning. But not every metal layer is the same, so even at 14nm they don’t all require EUV. And not everyone’s definition is the same for 14nm. So a chip described as 10nm might have a 14nm BEOL, which means that it could be developed using single patterning for the contacts, while another chip with a 10nm BEOL and 10nm finFETs would require double patterning.

But even if EUV doesn’t materialize in time to be cost-effective for metal 1 and metal 2 (it was supposed to roll out at 45nm), that doesn’t mean scaling will stop. The adoption of atomic layer deposition and atomic layer etch offer very different approaches to solving the same problems. They also could serve as complementary technologies to improve the effectiveness of either EUV or 193i. Line edge roughness disappears at 5nm using ALE, but it’s possible that future chips won’t use lithography at all. There are other technologies waiting on the sidelines, including directed self-assembly. Even on the litho front, there is work underway with nanoimprint and multi-beam e-beam.

Advanced packaging adds another wrinkle. How does anyone define a heterogeneous collection of chips developed at different process nodes? If the most advanced chip in a package was developed at 7nm, does that mean it’s a 7nm package, or a 180nm package because the analog parts were developed using older nodes? The definition of progress in advanced packaging is less about node numbers and more about performance, power and cost for specific markets. Just as having eight cores doesn’t improve the performance of a single-threaded software application, developing a chip at 7nm isn’t necessarily better for solving a problem than one developed at 28nm.

In fact, DARPA compared the performance of an advanced package at 130nm with one developed at 28nm and found them comparable. So far, there are no such comparisons between finFETs and other packaged approaches. Nevertheless, those numbers may prove far more meaningful than line widths or process nodes.

With the end of the ITRS roadmap—the last iteration was rolled out last spring—and the introduction of multiple roadmaps for different market segments, it’s time to develop new terminology that’s more relevant. Technology is getting more complicated, and the problems that need to be solved are becoming layered and nuanced. Within that context, the semiconductor industry needs a current set of definitions to define progress, not a single metric that dates back to 1965. Device scaling will continue, but defining them with Moore’s Law is no longer relevant.

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