Top Stories

Incremental Design Breakdown
How much value comes from reuse? While still a necessary part of most companies’ methodologies, the advantages are diminishing.

How To Justify A Data Center
Tipping the scale in favor of a massive on-premise compute farm is becoming more difficult.

Planning EDA’s Next Steps
Cadence CEO Anirudh Devgan talks about everything from AI and advanced packaging to continued scaling, an increased focus on R&D, and new opportunities.

Blogs

Technology Editor Brian Bailey argues that product naming is often irrational, but when it comes to standards, extra care should be taken. It often isn’t, in UCIe: Marketing Ruins It Again.

Cadence’s Frank Schirrmeister explains how machine learning interacts with chip design in different ways, in Autonomous Design Automation: How Far Are We?

Synopsys’ PV Srinivas digs into why integrating IR signoff within the place-and-route stage reduces costly manual ECOs, in Overcoming The Growing Challenge Of Dynamic IR-Drop.

Siemens EDA’s Pradeep Thiagarajan and Scott Guyton look at the benefits of frequency-domain periodic large and small signal analyses, in The Value Of RF Harmonic Balance Analyses For Analog Verification.

Codasip’s Philippe Luc cautions that finding one bug should be a hint to search for more of them in the same area, in Improve Your Verification Methodology: Hunt Bugs Flying In Squadrons.

Renesas’ Marta Martínez Vázquez defines the different types of radar and how they’re used to improve a car’s safety, in Radar For Automotive: Why Do We Need Radar?

Sponsor White Paper

Siemens EDA’s Full-Flow Portfolio Helps Engineers Achieve Optimum IC Design Verification Efficiency
Improving efficiency in analog design.

Newsletter Signup

Find our email newsletter signup page here.