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Siemens EDA’s Full-Flow Portfolio Helps Engineers Achieve Optimum IC Design Verification Efficiency

Improving efficiency in analog design.

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A quick overview of the front-end flow using the S-Edit schematic capture environment will be covered in this white paper, followed by a more detailed description and steps for using the Analog FastSPICE (AFS) platform simulator to go through the verification of a basic amplifier design.

Greater efficiency in analog design verification can now be achieved using our enhanced inter-tool communication in Siemens EDA’s full-flow design environment. Integrating S-Edit, AFS, and EZwave helps engineers achieve an optimum IC design outcome. The tight integration with the EZwave calculator allows for easy construction of advanced expressions and pre-simulation or post-simulation measurement modifications that are all stored in states under a schematic test bench.

S-Edit
S-Edit seamlessly integrates with all Siemens simulator offerings through an intuitive and highly customizable GUI. S-Edit is very easy to use out of the box, eliminating the steep learning curve often required when switching tools. The comprehensive and customizable toolbar at the top of S-Edit enables easy access to many design entry shortcuts and accelerates productivity as there is no need to look under complicated sub-menu and drop- down options. The libraries and cells associated with the design, the command window, and properties associated with an instance or test bench are conveniently located in S-Edit and can be detached and easily reconfigured to suit any work style or display area.

Op Amp design
A simple schematic is drawn in S-Edit for an eight transistor, two-stage operational amplifier (op amp) design implementation. The dummy devices are drawn at the bottom to construct a complete rectangular, common centroid layout for the NMOS current sinks.

Simulation Setup
The Simulation Setup allows the user to set up options and simulation test benches for various types of analysis and can be launched using the relevant toolbar button.

From the Simulation Setup menu, test benches can be created using the Sim test bench pulldown. Once a simulator is selected, all relevant simulation options and analysis on the GUI adapt accordingly. S-Edit supports three simulators: T-Spice, Eldo, and AFS. For this design several DC simulation test benches have been created. A schematic test bench can be associated, with several different simulation test benches, all created, renamed, copied and saved under this menu.

It’s worth noting that there are no hidden options or popup menus, and everything is shown on each corresponding sub window in the Simulation Setup. Selecting an option shows a brief description from the user manual at the bottom.
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