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Planning EDA’s Next Steps

Cadence CEO Anirudh Devgan talks about everything from AI and advanced packaging to continued scaling and an increased focus on R&D and new opportunities.

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Anirudh Devgan, Cadence’s new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what’s next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging.

SE: Where does EDA need to improve?

Devgan: We have made it much easier to design chips versus five years ago, but we still have more to do. System and chip design can be aided with 3D-IC and with the use of AI. At the same time, we want to make sure the core engines are always optimized for the latest design requirements. The big semi and systems companies want best-in-class tools, but they also want a comprehensive flow. That flow is one area where EDA has room to evolve. In the past, customers would put things together themselves in a zigzag flow versus a truly integrated flow. We have invested massively to develop full flows in digital, in verification, in custom/analog, and in system analysis. Creating flows is similar to what enterprise software companies have done. The EDA industry needs to provide holistic solutions that can reach across the spectrum of different verticals. So, for example, we’ve invested a lot of resources to ensure our 3D-IC flow includes analysis, packaging, digital, and analog tools in a single solution. Previously, you’d have to put together flows from four different product areas, and maybe across different companies, and they didn’t work together in a seamless fashion. Going back 5 or 10 years ago, Cadence had gaps in its offering. All of those gaps are gone now.

SE: The foundries used to have enough margin in their processes to be able to fix a lot of problems, and any other issues could be worked out over time because many chips had long lifetimes and huge volumes. Increasingly, because chips are now domain-specific and made in smaller batches with less margin, solving any issues has to be done much further left in the flow. How is it working with the foundries these days?

Devgan: On the foundry front, we’ve had a partnership with TSMC for a very long time, Samsung over the last few years, and now we’re doing more with Intel. In previous discussions some time ago, the role of EDA wasn’t as prominent, but that’s been changing. The early engagement conversations should include the customers, the foundries, and EDA. This three-way equation is one reason why these big systems companies have been very successful in their custom chip development. You need to leverage this equation in the best way possible. There are a lot of EDA tricks to get the full value out of 3nm, and you will see the foundries describe the flow to get the full PPA benefit. The same thing is true with 3D-IC. The role of EDA becomes more critical as we go to lower nodes and to 3D-IC, and that’s something more and more customers are realizing.

SE: Does security start fitting into the flow now, too? And if so, where and how?

Devgan: Security and safety are critical in all aspects of the flow, but particularly in verification. To address this, we launched a verification platform for safety and security. When it comes to vertical markets, while security and safety are very prominent in the automotive space, in general, the verification flow has to account for these considerations. Of course, some IP elements are also needed for security. What I also find is that verification can be a differentiator. Whether it’s a systems company or a semi company, verification has a huge impact on productivity and competitiveness. It’s always been important to the industry, but now it’s even more critical. And verification combined with the hardware platform for software bring-up is a key part of the ‘shift left’ paradigm. When you look at big companies, those with more advanced flows do software bring-up even before they do RTL freeze, which was not possible before. With domain-specific architectures, designers are doing more software bring-up, and more safety and security, and verification is where all these things come to a head. We see this even in a high-growth market — the verification market is growing, and the use of verification hardware platforms is growing. The old idea of, ‘It’s not what you design, it’s what you verify,’ is getting more critical.

SE: Advanced packaging never took off the way Cadence expected in the 1990s. In fact, it took a couple more decades before it became essential. Where do you see the market heading now, and what kinds of problems are you seeing?

Devgan: We’ve had packaging forever. We even created a flow about five to seven years ago, and it didn’t quite take off. But now, as the industry is moving from monolithic to more modular design, advanced packaging plays a huge role there and is growing rapidly.

SE: Is that because there are only so many more clicks on the Moore’s Law path before it becomes way too expensive?

Devgan: Let’s talk about Moore’s Law, which means a lot of different things to people. This is no longer classical silicon scaling, which was what it used to mean. I would argue that Moore’s Law for the better part of the last 10 years has not been driven by pure silicon scaling. What is driving the scaling of system performance now is the ability to put more components on the chip. We used to have one CPU running at 3GHz. Now there are eight CPUs at 3GHz, and the software has to take advantage of these. That’s why, for years, we have done parallel computing. The advantage is in the integration, not in the speed of a single component. Scaling is increasingly through putting more components on the chip, not necessarily through them getting much faster.

SE: And packaging is the next logical extension?

Devgan: Yes, and that was always possible. But there is more integration at the package level now. The question is whether customers will use 2.5D or vertical stacking. With 3D-IC, one of the biggest issues is thermal. Because you are generating a lot more heat, you have to dissipate that, so thermal floor-planning is required. Four pieces have to come together to make this work effectively — system analysis, packaging, analog, and digital, and we provide this in our new Integrity 3D-IC platform. This enables us to help accelerate our customers innovation, as many of our large customers are increasingly integrating very complex chips with heterogenous functionality into a single package.

SE: We talked a while ago about extending what the definition of the system is because issues on a chip can be expanded to a complete system, such as a car or data center. Are the tools you develop now getting used on a much broader basis? Have other companies that have never really developed chips started to look at these tools because of all the stuff they’re trying to pack into a system or a system of systems?

Devgan: Yes, because the silicon and systems are merging. One example of this is 3D-IC, but that’s tip of the iceberg. It’s the chip designer’s first exposure to the system. But if you come from the OEM side, like if you’re making a washing machine or a car, the first thing you see that is electrical is a PCB. The PCB becomes critical. And then the system analysis goes along with it. We have also expanded our systems portfolio to include computational fluid dynamics (CFD), and you need CFD for thermal because half the problem in thermal is the flow, not just the generation. All the systems companies, such as car companies, do fluid dynamics simulations for the car. And now we have customers such as Blue Origin. The system companies are doing more silicon, and we are moving up the product stack to sell them simulation software in and around silicon. It’s this whole CFD plus electromagnetics plus packaging/PCB plus silicon. And that’s where the issues are — even in the car. You see all these advanced car companies designing them for the best drag coefficient plus all the electrical challenges. This is why we got into CFD. We made two acquisitions last year because of the merging of systems and silicon, and the merging of electrical and mechanical. And now we want to do more computational things on the systems side, which includes simulation, because that’s one of our core competencies, and it’s also more profitable. There are other parts of the systems space, such as the actual design of the mechanical elements, where we can build partnerships, as well. The simulation side is the most critical now, and on the data side, we want to do more, too.

SE: Chip design is now vertical, planar, and there are elements of reliability over time, and all of those elements are variable by industry and by application. So instead of just shifting left, design now needs to incorporate data from the field, as well. How does this affect your strategy?

Devgan: This is what drives opportunity. Everybody wants to expand. But you want to expand in your vector of strength. So first of all, the core EDA business is going gangbusters. Silicon design revenue is going up for silicon companies, and all the systems and data fall under computational software. We are expanding, but not into areas that are not connected to what we know. The real strength we have is computational software — even AI. A lot of our current R&D development involves AI because we have done all this computation software for years in EDA. Matrix multiply and conjugate gradient are well-known methods in EDA. With simulation, there’s an algorithmic angle. All the CFD and finite elements are matrix inverses. Typically, if you do a thermal simulation of a phone, which is a big problem, 30 million x 30 million is considered a huge size. You have to simulate 30 million variables for them. It’s a huge thing for the system simulation company, but in EDA we have done this for 30 years. At 3nm and 5nm, we are already solving problems 50 billion x 50 billion on a chip. They have all these transistors and power grids. So we’re taking those algorithms, which are a thousand times more capacity, and applying them to a problem that is critical and growing at the system level. There is a customer synergy, but there is also an algorithmic and know-how synergy. Although it’s complicated and difficult, we are still swimming downstream. This is the real opportunity for EDA — leveraging this computational strength not just in semiconductors, because we got trained over the years, but also in systems and data. This can go on for 10 years or more, and we are in a great position to do that.

SE: If you look at Apple’s M1 chip, that is a successful example of hardware-software co-design and a heterogeneous architecture. Are you hearing about similar types of improvements in other places?

Devgan: Absolutely, and we can play a role in that. There is software bring-up where designers leverage hardware platforms early with the software driving the silicon design, as well as heterogeneous compute because you’re combining CPUs, GPUs, accelerators, and these are very big chips. And over time, we will start seeing some 3D-IC designs from other companies. We already have proven this with a few leading customers, and over the next five years, we will see more and more companies moving in that direction in multiple vertical markets. The same tools, capabilities, and foundries are available to all companies. We are still at the beginning of this shift.

SE: Where do chiplets fit into this picture? Is your core benefit the infrastructure of that flow and all the pieces that need to be integrated into it? All of these components will need to be verified individually and together.

Devgan: We have a platform to do that, and it has analysis on top. The benefits of chiplets are the same that we’ve talked about for 20 years, but the benefits were previously not fully realized. IP reuse has been more of a big buzzword, but it can really happen with chiplets. For example, if you have four chiplets in a package, you can really do IP reuse more efficiently. So for a different chip, maybe three of them don’t change all the way to manufacturing. This goes to the next level as a real savings, but you do need the platform and the IP to go with it. Our Integrity 3D-IC Platform ties all this together, and our Cadence Cerebrus Intelligent Chip Explorer adds the AI element to do chip design faster. In the past, EDA only focused on making the tools great, but we didn’t have the intelligence from one run to the next because each run was independent. With AI and reinforcement learning—and AI can mean a lot of things—but for this application it is perfect. We tried to automate the search of these design options and tool options from one run to the next. This adds a huge benefit—sometimes 10% to 20% PPA improvement, in addition to the huge productivity benefits.

SE: What is interesting about the chiplets market is that basically you’re unbundling the development time on each one of these chiplets. It’s no longer time-constrained, and the parts can be pre-verified. But the hard part is putting it all together and integrating it, right?

Devgan: Yes, and the decoupling is more like parallel algorithms. With any algorithm, designers always check what the synchronization points are and look at how much is parallel and how much is sequential. The good thing about chiplets is that the amount of synchronization goes down because if you do it on an SoC, you could have parallel development. However, designers still have to assemble, sign off, and tape out the full chip. The big difference is they’ve moved the parallelism up to the packaging level. You have more parallelism in the design flow, and more reuse. And then the integration happens at the packaging level, maybe after silicon. It reduces the bottlenecks of Amdahl’s Law in terms of parallel computing in the customer space. Designers can run things in parallel more often and then develop the right packaging environment to put it together. There are some performance benefits because you can put more things together with chiplets. The biggest benefits are design time, parallelization, and reuse.

SE: In your new role as CEO, you’re now looking at what pieces are missing out of this puzzle. What do you have to fill in?

Devgan: I became president in 2017, and we put together our Intelligent Design Strategy at that time. Of course, it takes a few years to fully realize the benefits. And now I have added responsibility as the CEO. But the strategy has been in place, and our focus is on accelerating our momentum. We are continuing on that with some of the acquisitions we’ve made, and pushing into new areas like CFD. We are always looking at acquisitions, if they fit, to further our strategy. We have all the pieces in place and just have to continue working to accelerate adoption from here. And if some additional M&A happens, that’s great. At the same time, we continue to invest about 40% of revenue in R&D, and I feel pretty good about the strengths of the different groups.

SE: That number is astounding to most companies. They would just look at that and say, ‘You must be kidding.’

Devgan: Yeah, and we have done this successfully for about 10 years now. We have the highest investment in R&D, and we have roughly a 37% non-GAAP operating margin. We are an engineering-driven company, with 80% to 90% of our employees being engineers. Either they are in R&D, or they are application engineers (AEs). Our margin used to be 26% or 27% not too long ago, and it has gone up to 37% because of our very disciplined execution. And we can still continue margin expansion. When we invest about 40% in R&D, we have an investment pool that we keep on the side, and every year we invest that money in some new projects that can drive future growth. It’s very important to make the right moves. The general managers of our four business groups all have technical backgrounds, which is necessary to avoid losing your way. We want to make sure our senior leadership talent always knows what is happening in the industry, and we keep talking directly to customers. We need to enable and empower people who are engineers and technical, but who still talk to customers and who have good communication skills. If you just have customer skills and don’t know what to do from a technology standpoint, it can be problematic. In our case, 40% of revenue has to be used properly. Otherwise, it doesn’t generate future growth.

SE: Every company has made investments where it took much longer to pay off than expected, right?

Devgan: Yes, and we are patient because there are no short-term financial pressures. Financially, we are run well, revenue is good, and we manage R&D well. If it takes one year, three years, or five years for something to take off, we adjust accordingly. And when we invest, we invest small at first and test out the thesis. We’re investing in quantum. Is it going to take off? I don’t know. But we can be patient because of our ratable EDA business model, and this core business is strong. One piece that is critical is the talent. In the end, it’s all software, and that’s driven by very capable people. We also have to keep encouraging more people to join the EDA industry. We’ve started all these university programs to hire fresh talent, and we’ve set up chairs at universities like MIT, CMU, Berkeley, and Stanford.

SE: Are the systems companies, which are now developing their own chips, using commercial EDA tools? Or are they developing their own, like IBM, TI and Intel used to do?

Devgan: Over time, the use of internally developed tools by customers has come down. Some of the new hyperscalers are doing some development, but a lot of it is built on top of commercial tools. Sometimes the customers will do their own floor-planning tool or something like that, which is design-specific, but the overall trend is moving more toward commercial tools.



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