Special Report
EDA Looks Beyond Chips
System design, large-scale simulations, and AI/ML could open multi-trillion-dollar markets for tools, methodologies, and services.
Top Stories
Dealing With AI/ML Uncertainty
How neural network-based AI systems perform under the hood is currently unknown, but the industry is finding ways to live with a black box.
Is There Any Hope For Asynchronous Design?
This approach has long held promise, but never managed to deliver. Is there a fundamental problem, or is it just bad luck?
NoCs In 3D Space
The network on chip has become essential for complex designs, but it needs to evolve to support 3D designs and enable the integration of chiplets.
Multi-Die Design Pushes Complexity To The Max
Continued scaling using advanced packaging will require changes across the entire semiconductor ecosystem.
Videos
Cache Coherency In Heterogeneous Systems
Why maintaining flexibility in coherency is essential in heterogeneous designs.
Challenges In RISC-V Verification
How to debug a multi-core chip and ensure it will be cache coherent and secure.
Blogs
Technology Editor Brian Bailey suggests that although it is great to see the DAC conference come back to life, EDA companies need to do something about the show floor, in Revitalizing DAC.
Siemens’ John Ferguson shows how to glean useful information well before all the details of an assembly are known, in The 3D-IC Multiphysics Challenge Dictates A Shift-Left Strategy.
Axiomise’ Ashish Darbari explains how formal verification can help improve chips, in Verification In Crisis.
Arteris’ Frank Schirrmeister tracks the race to centralized computing, in The Path Toward Future Automotive EE Architectures.
Synopsys’ Andrew Appleby explores the co-optimization of foundation IP and design flows for new transistors, in How To Get The Most Out Of Gate-All-Around Designs.
Cadence’s Anika Sunda looks at controlling the access to physical memory addresses, in Exploring The Security Framework Of RISC-V Architecture In Modern SoCs.
Keysight’s Ben Coffin digs into how AI will be used in just about every subsystem of 6G networks, in How 6G Research Will Revolutionize Mobile Experiences.
Sponsor White Papers
Reduce 3D-IC Design Complexity: Early Package Assembly Verification
Verifying and debugging complex multi-dimensional systems earlier in the flow using multi-physics analysis.
Key Critical Specs You Should Know Before Selecting A Function Generator
Function generators are not built the same.
Bridging The Gap Between Industry And Academia
Cadence facilitates the sharing of technology expertise with universities, research institutes, and industry advisors.
Rigorous Correlation Methodology For PCIe 5.0 & PCIe 6.0 DSP Based IBIS-AMI Models
A step-by-step correlation method adapted for DSP-based PCIe 5.0 & PCIe 6.0 IBIS-AMI models to measure and directly correlate raw errors out of the DSP on a test setup that is based on the receiver stress eye methodology of the PCIe standard.
How To Scale Application Security Across The Enterprise
Explore the challenges of managing software application risk at enterprise scale.
Aeonic Generate GGM High Performance SoC Clock Generation Module
The sea of processors use case.
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