Top Stories
Shift Left, Extend Right, Stretch Sideways
Development flows are evolving as an increasing number of optimization factors become interlinked. Shift left is just one piece of it.
The Good And Bad Of Chip Design On Cloud
Designing chips with the help of the cloud is progressing, but users still want greater flexibility in tools licensing and other issues.
Tradeoffs Between On-Premise And On-Cloud Design
Which companies are using the cloud and why, and where are the hidden pitfalls.
Large-Scale Integration’s Future Depends On Modeling
The progeny of VLSI is 3D-IC and a range of innovative packaging, but all of it has to be modeled to be useful.
Video
Using AI To Close Coverage Gaps
Why AI, when to use it, and what benefits it brings.
Blogs
Virtual conferences are in the rear-view mirror, but Technology Editor Brian Bailey is not convinced in-person conferences should continue, in Are In-Person Conferences Sustainable?
Expedera’s Pat Donnelly looks at increasing NPU utilization by optimizing the flow of activations through a network, in A Packet-Based Architecture For Edge AI Inference.
Movellus’ Barry Pangrle discusses how to regain lost power and performance, and what to watch out for when you do, in Managing Voltage Variation.
Arteris’ Frank Schirrmeister predicts that AI, chiplets, and increasing integration mean design methodologies could look very different in the next decade, in DAC 2023: Megatrends And The Road Ahead For Design Automation.
Siemens’ Dina Medhat contends that deploying physical verification techniques in isolation will not solve the challenges of densely packed designs, in Context-Aware Analysis Can Automatically Protect Critical Nets And Devices During Fill Insertion.
Keysight’s Sarah LaSelva foresees that a combination of large data sets and complexity will make wireless networks ripe for AI optimization, in Solving 5G And 6G Challenges With Artificial Intelligence.
Codasip’s Zdeněk Přikryl suggests enabling a compiler to use both standard and custom instructions automatically and wisely, in Re-targetable LLVM C/C++ Compiler For RISC-V.
Synopsys’ Taruna Reddy finds that distributed simulation enables a large job to be run in smaller parts, in New Technology Accelerates Multi-Die System Simulation.
Cadence’s Yang Zhan explains why network speed is one of the most significant limiting factors for generative AI, in 224G SerDes Trend and Solution.
White Papers
Placement And CTS Techniques For High-Performance Computing Designs
Maximizing performance for high-performance computing chips.
How To Boost ATE Power Supply Throughput
How test engineers can increase ATE system throughput to reduce costs.
The Road Ahead For SoCs In Self-Driving Vehicles
A scalable neural processing technology based on co-designed hardware and software IP for heterogeneous SoCs may help lower the Level 3 hurdles.
Synchronous Die-To-Die Signaling Using Aeonic Connect
A single-cycle die-to-die solution that uses three to five times lower power than existing standards.
New Research eBook
Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
Chiplets may be the semiconductor industry’s hardest challenge yet, but they are the best path forward.
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