Systems & Design

Synchronous Die-to-Die Signaling Using Aeonic Connect

A single-cycle die-to-die solution that uses three to five times lower power than existing standards.


This paper presents a system providing accurate clock alignment for on-die and die-to-die synchronous circuits. A low-frequency reference clock provides an accurate timing reference with low power consumption, while distributed delay lines align the endpoints of loosely constrained clock trees. For on-die clocks, this synchronization strategy severs the traditional relationship between power and skew. For die-to-die interconnect, this allows single-cycle latency flop-to-flop synchronous communication with lower power and lower complexity than traditional clock-forwarded schemes. Our test chip in TSMC 12nm demonstrates a power efficiency of 0.2pJ/bit without aggressive scaling of the pad ESD.

Presented at CICC 2023, Movellus explores a single-cycle die-to-die solution that is 3-5x lower power than existing standards.

Register here to download the paper.

Leave a Reply

(Note: This name will be displayed publicly)