tag: clock trees

Synchronous Die-to-Die Signaling Using Aeonic Connect
By Movellus - 26 Jul, 2023 - Comments: 0

This paper presents a system providing accurate clock alignment for on-die and die-to-die synchronous circuits. A low-frequency reference clock provides an accurate timing reference with low power consumption, while distributed delay lines align the endpoints of loosely constrained clock trees. For on-die clocks, this synchronization strategy severs the traditional relationship between power an... » read more

Conquer Placement And Clock Tree Challenges In HPC Designs
By Janet Attar - 11 May, 2023 - Comments: 0

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging. Designers need digital implementation tools and methodologies that can solve the thorny issues in HPC designs, including placement and clock tree challenges. Placement and clock tree synthesis are c... » read more

Using Less Power At The Same Node
By Brian Bailey - 14 Mar, 2019 - Comments: 0

Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

Why Inductance Is Good for Area, Power and Performance
By Magdy Abadir - 12 Mar, 2018 - Comments: 0

By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design... » read more

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