tag: clock tree

The Vulnerability of Clock Trees to Asymmetric Aging
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations" was published by researchers at Israel Institute of Technology and The Hebrew University of Jerusalem. Abstract "Ensuring integrated circuits (ICs) operate reliably throughout their expected service life is more vital than ever, particularly as they become increasingly central to mis... » read more

How Big A Deal Is Aging?
By Brian Bailey - 17 Oct, 2024 - Comments: 0

Nothing lasts forever, but in the semiconductor world things used to last long enough to become obsolete long before their end of life. That's no longer the case with newer nodes, and it is raising concerns in safety-critical markets such as automotive. Being able to fully understand what happens inside of chips is still a work in progress, and analysis approaches are trying to keep up. Unti... » read more

Synchronous Die-to-Die Signaling Using Aeonic Connect
By Movellus - 26 Jul, 2023 - Comments: 0

This paper presents a system providing accurate clock alignment for on-die and die-to-die synchronous circuits. A low-frequency reference clock provides an accurate timing reference with low power consumption, while distributed delay lines align the endpoints of loosely constrained clock trees. For on-die clocks, this synchronization strategy severs the traditional relationship between power an... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes
By Aakash Jani - 01 Aug, 2022 - Comments: 0

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

Another Tool In The Bag
By Ann Mutschler - 06 Nov, 2014 - Comments: 0

Clocks can account for 25% to 40% of total dynamic power consumption in a complex chip, so when looking for areas to reduce power, the clock tree network is a good place to start. Structurally, it is certainly possible to have single-bit flip flops with a clock that connects to every one of the flip flops, and the power in general is proportional to the number of buffers in the clock tree on... » read more

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