Top Stories
Analog Migration Equals Redesign
Advanced nodes are forcing design teams to make tradeoffs at each new node and with each new process.
Get Ready For Verification 3.0
Functional verification is going through many changes, and one of EDA’s leading investors sees lots of new possibilities for startups.
CEO Outlook On Chip Industry
Part 1: New opportunities and potential pitfalls in automotive, 5G, connected intelligence and infrastructure as a service in EDA.
Video
Tech Talk: Traceability In Functional Safety
Regulations, standards and liability.
Blogs
Editor In Chief Ed Sperling observes that new technology is beginning to break down barriers between form and function, with huge implications, in The 3D Printing Revolution.
Technology Editor Brian Bailey questions whether a vendor can differentiate itself based on the quality of its constraint solver, in Commoditizing Constraints.
Mentor’s Matthew Ballance explains how dynamic constraints can make portable stimulus test intent more flexible, modular and reusable, in Making Declarative Modeling Modular: Portable Stimulus Introduces Dynamic Constraints.
Cadence’s Frank Schirrmeister finds that after 20 years, ESL concepts have been robustly adopted, in Electronic System-Level Design: Are We There Yet?
OneSpin’s Tom Anderson contends that formal verification is at the heart of finding both introduced and random errors, in A Combined Design And Verification Flow For Safety-Critical Designs.
Synopsys’ Eric Huang demonstrates a host and device operating together at full speed, in First Look At USB 3.2.
Aldec’s Sunil Sahoo shows how to slash latency and improve performance to win over the competition, in Speeding Up High-Frequency Trading.
