Top Stories

Verification In The Open-Source Era
What does open-source verification mean in the context of a RISC-V processor core? Does it provide free tools, free testbenches, or the freedom to innovate?

Demand For IC Resilience Drives Methodology Changes
New ways of connecting design, verification, test, and in-field data are needed for longer lifetimes and more critical applications.

Waiting For Chiplet Standards
An ecosystem is required to make chiplets a viable strategy for long-term success, and ecosystems are built around standards. Those standards are beginning to emerge today.

Blogs

Technology Editor Brian Bailey asks if EDA has failed to innovate, or if the semiconductor industry has shown an unwillingness to adopt new tools and methodologies. As always, the answer is somewhere in between, in Stuck In A Rut.

Synopsys’s Kiran Vittal explains how to find and fix errors efficiently by using coding assistance for SystemVerilog, in Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity.

Cadence’s Frank Schirrmeister takes a look at how defense contractors and the US Air Force are increasing verification confidence and deploying digital twins, in Digital Transformation In Aerospace And Defense Applications.

Siemens EDA’s Greg Curtis and Ahmed Ramadan, and GlobalFoundries’ Ninad Pimparkar and Jung-Suk Goo, call for enabling a standard simulator-agnostic interface for aging modeling, simulation, and analyses, in Aging Analysis Common Model Interface Gains Momentum.

Aldec’s Farhad Fallahlalehzari examines why FPGAs were used in the Perseverance rover for applications such as radar transceiver, navigation systems, motor controllers, and computer vision applications, in Processing With FPGAs On Mars.