Processing With FPGAs On Mars

Tasked with finding life in the form of microorganisms, the rover Perseverance landed on Mars at about 04:00 EST on February 18, 2021. The rover has multiple sensors and cameras to collect as much data as possible and, due to the volume of live data being recorded and the long data transmission time from Mars to Earth, a powerful processing system is essential.

However, whereas early Mars rovers were equipped mainly with CPUs and ASICs as the processing units, FPGAs are taking on much of the workload in Perseverance. Let’s consider why that is the case.

FPGAs’ responsibilities on Perseverance rover

FPGAs are used in newer Mars rovers for different applications such as radar transceiver, navigation systems, motor controllers and computer vision applications. Perseverance utilizes an almost decade-old FPGA technology (Xilinx Virtex-5) as one of the main processing units. This unit is first responsible for rover entry, descent and landing on Mars and then it is programmed for computer vision tasks by NASA engineers from the Earth. Other units on Perseverance such as UHF transceivers, radar, X-ray (identifying chemicals), and cameras are controlled with XQR4VFX60 and XQR2V3000 FPGAs.

One of Perseverance’s most important units is SHERLOC, a rather apt acronym for Scanning Habitable Environments with Raman & Luminescence for Organics & Chemicals. It uses cameras, spectrometers, and a laser to search for organics and minerals that have been altered by watery environments and may be signs of past microbial life. SHERLOC’s functionality is largely implemented in a unit, which is a sensor fusion module (combination of a camera, spectrometer, and laser) with a purpose of fine-scale detection of minerals, organic molecules, and potential biosignatures. This unit is also run by XQR2V3000 FPGA.

Fig. 1: Perseverance Mars rover.

The interesting point about the Perseverance is that by using FPGAs to implement well-optimized machine learning and computer vision algorithms, it is achieving much higher performance levels (circa 18x) than Curiosity rover which landed on Mars on August 5, 2012 is still active on Mars.

Benefits of using FPGAs in space

Here are some of the main reasons why FPGAs were the best choice for Perseverance’s most intense processing functions:

• Re-programmability: The Opportunity rover started its tour duty on Mars in 2003, a tour which was ended by a Martian dust storm in 2018. The Curiosity rover (as mentioned, its tour started in 2012) is still active. The life of rovers is long enough that the processing system architecture must accommodate reconfigurability to let NASA’s engineers change/optimize it anytime they need it. FPGAs provide direct access to firmware which results in re-programmability on the fly.
• Low power: The lower the power consumption, the more the life expectancy of the rover would be. Being heavy and having several sensors, cameras, and motors, it’s very important to have a low power data processing unit which could become one of the most power-hungry units on the rover.
• Radiation tolerant: Cosmic radiation such as particles trapped in the Earth’s magnetic field, particles shot into space during solar flares (solar particle events), and galactic cosmic rays, can result in single event upsets and latch-ups (SEUs and SELs respectively) in digital circuitry. For this reason, radiation-tolerant FPGAs are used and tested extensively on satellites in the space for many years.
• Security: Deploying encryption algorithms into FPGAs hardware provides stronger security. (Of course, aliens are looking for a way to steal our data.)
• Cost efficiency and faster time-to-space: As there are many changes in the processing unit’s architecture during any space project’s development phase – there’s usually an imperative to hit a launch window – it is difficult to allow for the fabrication of an ASIC. Also, the cost of design, development and fabrication of an ASIC is very high comparatively.

However, even with the above benefits of using FPGAs, you could still have a relatively complex design verification process – if the most appropriate EDA tools are not used to automate the steps and provide you with the utmost confidence for the launch day.

RTL simulation before generating the netlist lets us find the errors in the design in an early stage which saves us a lot of time and money. After simulating, prototyping is what makes us completely confident about the accuracy of the design verification. This step requires a single to multi-FPGA prototyping board. If the design is not fit into a single chip, it must be portioned into multi-FPGAs which is problematic if it is done manually. This is when a design verification manager tool with multi-FPGA auto partitioning feature saves a fortune.

Fig. 2: Aldec FPGA/ASIC prototyping and emulation solution.