Special Report
Designing Electro-Optical Chips
Photonics is forcing EDA to verify not just chips, but the physics of light inside full electro-optical systems.
Rethinking Chip Verification
Specification engineering is gaining traction as a potential solution to the verification bottleneck.
Top Stories
Data Center Chokepoints Tied To AI, Political Pressure, Supply Chain
Technical, political, and supply chain challenges are complicating data center buildouts around the U.S.
Observability Is A Missing Layer In AI-Era Chiplet Design
In next-generation silicon, AI can interpret system behavior at scale, but only if observability is designed into the fabric as a first-class architectural capability.
AI In Chip Design: Lots Of Promise, Plenty Of Unanswered Questions
Where AI will be successful, who will benefit, and how that will affect the design process.
Video
Verifying Networks On Chip
Challenges increase significantly with chiplets and coherency.
Opinion
Change Is Tough
There has never been a time when change has become something everyone expects. Now we are figuring out what it means to us individually.
Sponsor Blogs
Baya Systems’ Nandan Nayampally shows how semiconductor policy shifts affect every company in the industry, regardless of size, in Chip Policy: The UK Vs. The US Vs. EU Vs. India.
Siemens EDA’s Keith Felton and Todd Burkholder detail why chiplet interface route planning, optimization, and predictive analysis are crucial for achieving PPAC goals, in Realizing The Future Of 3D-IC: Final Scenario And Sign-off.
Arteris’ Insaf Meliane shows how automated connectivity and a single source of truth accelerate SoC assembly while improving design quality, in Avoid The Hidden Bottleneck Of Integration At Scale.
Synopsys’ Frank Schirrmeister explores the emulation and prototyping hardware that’s taking center stage at DAC 2026, in From Future Vision To Running Hardware: Verification At DAC 2026.
ChipAgents’ Sidharth Kannan digs into the automation of repetitive, time-consuming behavioral model creation while keeping engineers in the loop, in Why Chip Engineers Should Care About AI-Created Behavioral Models.
Vinci’s John Bruggeman argues that engineering intelligence cannot remain fragmented across isolated AI models that understand only narrow slices of physical behavior, in The End Of Physics Silos In Engineering AI.
Cadence’s Niyati Singh explains how to translate stress and aging data into measurable design signals for determining whether circuits still meet reliability expectations, in Using Reliability Degradation Parameters To Drive Better Design Choices.
Keysight’s Joo-Ann Beh shows how to reduce patient risk and support regulatory readiness by demonstrating how a device performs in the presence of real world interference, in How Wireless Coexistence Testing Exposes Real‑World Medical Device Behavior.
Sponsor White Papers
Enhancing System Observability
Integrating real-time voltage telemetry and functional monitoring for deeper insights.
Accelerating AMS Verification With Mixed-Signal Visualizer
Reducing analog/mixed-signal debug time with a unified platform.
Bringing Design Data Management into the Developer Workflow
Bridging the gap between modern development environments and enterprise EDA data management.
Enabling Comprehensive CWE-based Assurance for RISC-V Processors
A scalable, Common Weakness Enumeration (CWE)-based security assurance methodology for third-party RISC-V processor IP.
Silicon Starts with Proven IP: eBook
Why IP strategy is now an architectural decision and how silicon-proven IP reduces integration risk, improves first-pass success, and accelerates time-to-market.
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