Chiplet interface route planning, optimization, and predictive analysis are crucial for achieving PPAC goals.
By Keith Felton and Todd Burkholder
Multi-chiplet packages contain thousands of connections between chiplets, interposers, and package BGAs. After optimizing this complex connectivity, designers must identify related signal groups (interfaces or buses) and plan their path from the chiplet bump field to target bumps or BGA balls. This involves managing multiple groups, considering available routing real estate and channels, and ensuring that electrical performance meets expectations and that interface protocols comply with specifications.
Traditional methodologies require manual or automatic routing without pre-planning, often resulting in bump field blockages, route congestion, channel blockages, inadequate signal performance, and failed interface protocol compliance. This leads to multiple rip-up and retry iterations, which tend to compromise route quality with excessive vias, increased route length, and signal integrity issues.
Fig. 1: A 3D-IC on a PCB requires thousands of connections between chiplets, interposers, and package BGAs.
Following the steps detailed in the first article in this four-part series on streamlining 3D-IC design, the fully floorplanned interposer and package substrate are ready for scenario completion. This involves chiplet interface route planning, optimization, and predictive analysis to ensure optimal power, performance, area, and cost tradeoffs. This is critical as it ensures the design meets all compliance requirements, thermal constraints, manufacturing, and testability readiness before physical implementation. Completing these steps reduces iteration cycles and accelerates time-to-production. We will also highlight chiplet-to-chiplet interface protocol compliance, with a specific focus on the Universal Chiplet Interface Express (UCIe) protocol.
During this stage of 3D-IC development, the design scenario is finalized before it can move to assembly verification and handoff.
Before detailed implementation, the designer must verify that chiplet-to-chiplet high-speed interfaces using Universal Chiplet Interconnect Express (UCIe) technology will meet protocol compliance based on the current design scenario. This involves analyzing serial-link channel interconnect plans using standards-based compliance analysis and vendor model-based IBIS-AMI simulation. Multiple physical parameters are explored to understand their impact on compliance. These include substrate materials, layer stackup, chiplet bump/microbump array, as well as trace dimensions, spacing, and breakout patterns.
Fig. 2: Innovator3D IC Protocol Analyzer checks a chiplets bump array breakout pattern using its integrated 3D electromagnetic solver.
The goal is to achieve pre-route level interface compliance by identifying and setting optimal physical design parameters. Once confirmed, the next critical step is to optimize the overall design using multiphysics analysis to ensure thermal and mechanical reliability.
When using an advanced integration platform, a key aspect of prototyping and planning heterogeneous chiplet integration is determining if the resulting scenario meets power, performance, area, and cost goals.
2.5/3D integration often combines heterogeneous chiplets with different process nodes and new interconnection technologies, introducing additional variables in design and verification. Multiphysics phenomena are integral to overall design success. Horizontal and vertical structures of 2.5/3D designs, interconnected by TSVs, TIVs, and micro-bumps/hybrid bonds, create a tightly coupled environment where heat dissipation, mechanical integrity, and electrical behavior interact complexly.
Postponing these analyses until late in physical implementation risks costly redesigns or performance and reliability failures. Traditional SoC design relies on high-level RTL, with many physical optimizations fixed early. 2.5/3D-IC complexity and physical coupling necessitate earlier feedback from physics-driven analysis during RTL and chiplet or package assembly floorplanning, enabling informed choices before constraints are locked in.
Only early, predictive multiphysics analysis can reveal and mitigate these risks cost-effectively. Continuous multiphysics evaluation must begin with chiplet floorplanning and continue through every design iteration. Each change to a floorplan, interface, or materials can introduce new thermal or mechanical stress concerns, requiring re-evaluation to maintain system reliability and yield.
Thermal management is the most important consideration for die-to-die interfaces in 2.5/3D-IC designs. Proximity of active dies leads to rapid heat accumulation and other risks, like thermal runaway, where ongoing heat generation degrades electrical performance and creates mechanical stress from varying thermal expansion rates. Differential expansion can warp dies and threaten interconnect reliability.
Fig. 3: The Innovator3D IC Integrator-driven multiphysics solution.
Once co-design optimization is complete, the design team is ready to plan for comprehensive testing. While die-level testing remains unchanged from 2D, 2.5/3D-IC packages require die-to-die interconnect testing and reruns of known-good-die tests for post-packaging defects. A 2.5/3D-IC DFT solution is an extension of the existing hierarchical DFT principle. But there’s one more level of hierarchy to consider: the stack level.
In hierarchical DFT, pattern generation is done at a lower level of hierarchy, then retargeted (or mapped) to a higher level. In 2D DFT, this is usually the die top level. In 3D DFT, a hierarchical solution never fully loads the entire stack. Core-level patterns are retargeted twice: to die top-level for wafer testing, and to stack-level “top” for stack testing. For efficiency, time-consuming pattern generation (especially ATPG) is executed once; retargeting is fast.
Additional 3D-IC testing issues include unintended DFT effects causing false failures in other dies. Heat from testing may impact adjacent die performance. While operational parameters like heat dissipation and power consumption are considered during design, combining instrument- or core-level patterns from different dies into a stack-level pattern can avoid unintended DFT failures. An effective DFT solution must allow composition of stack-level patterns from core- or instrument-level building blocks for various optimization goals.
The system-level netlist of a 2.5/3D-IC semiconductor package assembly is a key part of the design’s 3D digital twin. Before sign-off and export, the design team must ensure synchronized netlists for all devices (chiplets, interposers, substrates) with no outstanding connectivity ECOs. Any DFT logical connectivity additions or recommendations must be incorporated. Innovator3D IC Integrator’s built-in logical versus physical connectivity netlist visualizer and debugger, which accounts for internal device connectivity, helps designers visualize and debug logical or physical connectivity anomalies before sign-off LVS, avoiding ECOs. Innovator3D IC Integrator locates and highlights anomalies for early resolution. These include missing pins, superfluous pins, superfluous pins of foreign nets, and pins connected to the wrong net.
Fig. 4: Innovator3D IC Integrator’s connectivity visualizer and debugger.
With the design scenario complete and finalized, the next step is the formal process of design sign-off. The use of ASICs and chiplets from multiple processes and foundries increases complexity and the need for a process to ensure correct manufacturing and assembly within a single heterogeneously integrated, advanced package platform.
The core problem is the absence of formal verification processes for 2.5/3D-IC package design. This forces designers to navigate inconsistent processes, increasing risk and slowing time-to-market. The latest multi-chiplet heterogeneous integration platforms from foundries and OSATs enhance layer interactions, blurring traditional die-package separation. This necessitates a unified co-design flow with rigorous verification to ensure substrate/interposer compliance and correct assembly. Fortunately, OSATs and foundries are now providing PDKs and package assembly design kits (PADKs) for advanced integration platforms.
The first step then is for designers to perform substrate or interposer design rule check (DRC) verification against fabricator guidelines. This involves taping out the substrate/interposer in GDS or OASIS format and using a geometry-based DRC tool, like Calibre nmDRC, with the fabricator’s ruleset or PDK.
Next, the design team ensures that the complete assembly meets the requirements of the foundry or OSAT constructing it. Despite accurate machinery, tolerances must be considered for yield and reliability. Traditional IC-centric physical verification solutions are unsuitable for advanced package validation. Verification tools rely on GDSII or similar formats, which infer vertical placement and connectivity from layer mapping. This works for traditional IC design but breaks down in advanced packaging due to significant vertical displacement between geometries that might be interpreted as co-planar.
The next challenge lies in validating electrical connectivity across the assembly. IC design relies on SPICE for device-level connectivity and electrical simulations. However, SPICE infers connections from device lists and is too bulky for package design, which doesn’t deal with transistor-level data. Other formats, like AIF, represent pin connections. Without true devices, traditional LVS tools relying on SPICE-style netlists have nothing to check.
After validating the design assembly scenario with multiphysics analysis and upon meeting performance requirements, the next step is verification. This ensures the assembly is correct, matches the golden assembly netlist, and will function as intended. The more complex the design, the more crucial assembly verification becomes.
For a typical silicon interposer design where one foundry manufactures both interposer and chiplets, chiplet physical verification is established. The primary challenges are interposer DRC, LVS, and chiplet alignment and connectivity to the interposer. Siemens addresses this with an integrated solution: Innovator3D IC Integrator for planning and Calibre 3DStack for exhaustive 3D verification. This allows independent verification of complex multi-substrate assemblies.
Fig. 5: Verification capabilities of Calibre 3DStack.
The foundry provides interposer DRC and LVS as part of the standard PDK. However, chiplet alignment and connectivity to the interposer are challenging due to varying chiplet location and orientation, often left to the system-level designer. Full assembly verification becomes exponentially harder with multiple substrates, where no single manufacturer provides a full-system PDK. System-level designers need a reliable, automated approach to generate data for full assembly verification.
Ideally, this approach should account for the full assembly and be fully automated within the system-level design environment. Setup files from the Innovator3D IC Integrator prototyping and planning cockpit are loaded into Calibre 3DStack with a system source netlist, allowing independent DRC, LVS, and chiplet alignment/connectivity verification. This designer-centric approach is agnostic to different die technology nodes, substrates, and manufacturing vendors.
At this point, the design team has a completed, verified design assembly scenario that falls within performance margins and is ready for export. This typically involves exporting various hierarchy levels separately for detailed implementation.
The data exported for detailed physical implementation can vary based on the target tool, which may be from a different EDA vendor. Therefore, the planning and prototyping cockpit, such as Innovator3D IC Integrator, must export multiple data formats. Any changes to external interface locations or signal assignments during detailed implementation should be back-annotated to the master design assembly scenario model to ensure overall functional, logical, physical, and electrical continuity.
Manufacturing validation requires multiple test vehicles (typically 10+ per design) that mirror production design physical characteristics (layers, die placement, floorplans) but use specialized daisy-chain structures instead of functional netlists.
Manually creating daisy-chain structures across multiple substrates is time-consuming and error-prone. Innovator3D IC Integrator automates this, enabling quick and accurate generation and documentation of daisy-chain test vehicles. Implementing this sign-off and export methodology eliminates design iterations, reduces manufacturing risk, and accelerates time-to-market.
Fig. 6: A daisy-chain test vehicle example in Innovator3D IC Integrator.
UCIe is an open specification for die-to-die interconnects and serial buses between chiplets. It is considered the de facto standard for logic-chiplet-to-logic-chiplet communication. UCIe supports both organic 2D and silicon substrates, embedded bridges, and high-density fan-out RDL based substrates.
Early pre-route pathfinding analysis and optimization for UCIe interface channels are essential because they allow designers to proactively identify and mitigate potential signal integrity issues before committing to expensive and time-consuming physical layouts. It empowers designers to make informed decisions, avoid costly mistakes, and ensure successful, high-performance, and cost-effective implementation of UCIe chiplet-to-chiplet interfaces. It’s about building a strong foundation rather than trying to fix cracks after the building is complete. We will summarize the five steps of this process.
The first step is to explore the inter-chiplet UCIe physical channel parameters, including substrate material options and choices and potential layer stackups. It is also very important to explore the proposed chiplet bump array and metal route dimensions, spacing, metal thickness, etc. This gives the design team a level of confidence in achieving the desired performance and compliance against the protocol’s specifications, whether it is standards-based or vendor model-based IBIS-AMI simulation of serial links.
If a chiplet is already completed or being provided by a third-party, the ability to influence and optimize its bump array and signal assignments to more easily achieve compliance is removed. However, the bump array pin field and the associated UCIe serial link breakout patterns and structures need to be modeled and analyzed, as this has the greatest impact on data throughput and standards compliance. Typically, you will model the effects of physical objects that are defined in the UCIe package template by sweeping across a range of values.
Fig. 7: Example of parameters for a UCIe standard package template that can be analyzed.
The key parameters to control are return-loss, insertion-loss, differential-return-loss, and differential-insertion-loss. The design also needs to meet standards-based channel compliance. The goal is to achieve the lowest return-loss and insertion-loss for all the signals in the UCIe interface. This is done through the optimization of the physical parameters of the channel’s interconnect structure design objects, accomplished by running multiple case study simulations to understand what the optimal parameters are.
Before simulation can happen, you need to create a 3D electromagnetic (EM) model for each of your design scenario case studies. These models are created either using a full wave field solver or a hybrid field solver. This model is based on the selected UCIe template with the design objects, stackup, and layer materials set to their defined parameters. The generated 3D EM models, one for each scenario, will then be used for the simulation and UCIe protocol compliance.
Fig. 8: 3D EM model autogenerated from the standard UCIe template by Innovator3D IC Protocol Analyzer.
Standards-based compliance analysis involves verifying that your design adheres to the specific electrical, timing, and protocol specifications outlined in the UCIe standard document. At this early pre-layout phase, it’s always advisable to start with a standards-based compliance approach.
Once you know that you can achieve minimal compliance for your channels, you can utilize your vendor’s IBIS-AMI PHY model to perform a more detailed analysis of channel performance and tune the channel utilizing advanced equalization techniques, unique clock data recovery algorithms, or proprietary enhancements offered by a specific vendor’s PHY. These can significantly impact actual channel performance.
Innovator3D IC Protocol Analyzer supports both approaches, and we recommend that you use both types of analysis to achieve a robust high-performance design. By combining both approaches, you get the best of both worlds: the assurance of interoperability provided by UCIe standards compliance and the detailed, real-world performance prediction and optimization offered by vendor-specific IBIS-AMI models.
For UCIe, design space exploration (DSE) helps you navigate the vast number of design variables and their interactions to find the optimal channel configuration. Innovator3D IC Protocol Analyzer uses an AI powered SHERPA algorithm to efficiently explore large design spaces with as few simulations as possible, providing the fastest path to UCIe protocol compliance. Once DSE has been completed, the designer can select the best performing design scenario and validate it for compliance.
With the first four major steps of the 3D-IC design process completed (creating the 3D digital twin, pathfinding the optimal floorplan, finalizing the design scenario, and signoff and export), the design team is ready to perform substrate implementation strategies, finalize the substrate design, and tape out the fabrication mask set—which will be covered in the next article in this series.
Can’t wait? To dive deeper into how to improve your 3D-IC flow, please check out the new series of eBooks from Siemens on Streamlining 3D-IC design:
Todd Burkholder is a senior editor at Siemens DISW. For over 25 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of EDA technologies. Burkholder began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply