Top Stories

Pointing Fingers, Often In The Wrong Direction
Re-using or buying IP saves time, but the results aren’t always predictable. Here are several ways to improve your chances for success.

IP To Meet 2.5D Requirements
Widespread use of 2.5D is still at least a year out from becoming a viable option but specific technical requirements are being identified along the way.

Improving LP Verification Efficiency
Whichever method of power aware verification is chosen, don’t wait until three weeks before tapeout to do it.

Can HLS Be Trusted?
High-level synthesis has been around for years, but do engineers trust the results they get from using HLS and how well is it suited to low power?

Powerful Memories
First of two parts: As memory takes up a larger portion of the SoC, questions abound about what can be done to reduce power and improve performance.

Blogs

Editor in Chief Ed Sperling observes that power will force a massive re-education effort across the semiconductor industry at 16/14nm in FinFET Learning.

Executive Editor Ann Steffora Mutschler questions whether we are pushing available power around instead of truly saving it in Is My iPhone Hurting The Earth?

ARM’s Trina Watt puts a positive spin on screens and how smart they’re getting in The Rise Of Screens In Your Home.

Mentor’s Colin Walls says it’s critical for embedded developers to rethink how they approach embedded system design in Power Management Considerations For Efficient Embedded Systems Development.

Cadence’s Brian Fuller looks at the impact of 50 billion things drawing 1 watt and what to do about it in Google Project Ara And The Low-Power Imperative.

Synopsys’ Ken Brock looks at whether a single design kit can optimize all CPUs, GPUs and DSPs in One Design Kit?

Ansys-Apache’s Aveek Sarkar contends that an accurate, distributed package model is required to assure signoff quality results in FinFET-Based Designs: Power Sign-off Considerations.

Calypto’s Anand Iyer argues that that current methodology needs rethinking to address gross and fine-grain techniques and the best low-power logic structure in Low-Power SoC Design.

Atrenta’s Kiran Vittal examines the important ingredients of product CDC verification of both ASICs and FPGAs in Productive Clock Domain Crossing Verification.