FinFET-Based Designs: Power Sign-off Considerations

An accurate, distributed package model is required to ensure sign-off quality results.

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FinFET devices can operate at ultra-low sub-1V nominal supply voltage levels without impacting their delays. This allows for low power, higher performance designs needed for many of todays’ applications. These devices also have considerably higher drive strengths, allowing faster operating speeds. However, this can result in more localized di/dt current scenarios, and when coupled with more resistive and inductive chip-package power grid networks can result in higher levels of dynamic voltage drop or transient noise. The combination of lower supply voltages and higher voltage drop noise can be quite detrimental to the operation of FinFET devices.

In a previous blog, I discussed RTL-stage early power estimation methodology can help designers moving to FinFET-based designs understand where they need to optimize their designs to reduce dynamic power consumption. To achieve this, it is important to have an RTL power analysis flow that is predictable and consistent against gate level power numbers and to have a physical design-aware RTL power analysis.

In this blog, I will discuss another aspect of power analysis — the verification and sign-off of the power delivery network (PDN) across the chip, package and board — to ensure the robustness of the PDN design so that it can supply reliable and consistent voltage levels across the chip. Traditional PDN verification is performed by simulating the chip or parts of the chip using DC (static) and time-domain (dynamic) simulation techniques. DC or static analysis helps isolate gross PDN design issues and ensure that the design meets foundry specified reliability limits, such as those for electro-migration (EM). Static analysis turns on every device in the design and draws current based on the device’s size and loading. It has no direct correlation between the actual simulation condition and the real life working of the device.

In order to simulate a design for its actual operating mode or for a particular stream of software, dynamic simulation becomes necessary. In a dynamic or time-domain simulation, the devices switch as they would in real life when executing a particular software application. The current flow inside the chip, through the package, board and the capacitors, reflects a particular operating condition from one instance in time to another. Dynamic voltage drop analysis is able to correctly pinpoint and highlight issues in the design, such as poor interconnect routings, lack of decoupling capacitance, clustering of high power drivers in the same region, or the impact of dynamic voltage drop on device performance.

With reduced noise margins and higher sensitivity from power noise, it has become important for FinFET based designs to perform comprehensive dynamic voltage drop simulations. But unlike other sign-off simulations such as timing or DRC/LVS, dynamic voltage drop analysis cannot be partitioned and split because there is a considerable coupling effect across the chip and through the package. Splitting the design indiscriminately introduces significant inaccuracies. At the same time, design sizes continue to significantly increase. To manage the total turnaround times and to leverage the available computing infrastructure, it is necessary to use distributed simulation techniques that factor in the chip-package-PCB parasitics and the switching current across the chip in each partitioned run. This is important to ensure that the quality of results does not degrade from the distribution and parallelization and that the sign-off can be performed with confidence. For FinFET based designs that have reduced noise margins, the quality of result becomes additionally important.

As part of the dynamic power noise sign-off process, another thing to consider is the activity set that is used to simulate the design. Given the size of the designs and the required accuracy levels, it can be computationally prohibitive to perform large number of simulations. So judicious choice of the vectors is necessary to strike a good balance between sign-off coverage confidence and sign-off analysis closure time. Power being a statistical problem lends itself well to vectorless techniques. Statistical methods that generate “worst-case” switching scenarios are useful to identify PDN design weaknesses, to understand when a resonance condition can happen from chip-package/PCB coupling, and to predict high switching current conditions that can result in catastrophic failures or timing degradations in the chip. Next-generation statistical vectorless techniques that explore multiple different switching conditions in one simulation are becoming common as the complexity of designs continues to explode.

Another technique that is becoming increasingly common is the use of RTL vectors to drive the final gate level design power noise analysis. RTL power analysis flows can quickly identify activity modes that can create worst-case power noise conditions in the design by scanning large number of vectors and associated clock cycles. Power noise analysis flows can use the register level activity to determine the switching in every cell in the design and predict the voltage drop across the chip for each of these operating modes. These simulations are particularly useful to provide feedback to timing flows to understand which parts of the clock tree or which critical paths are most likely to get degraded.

For all these simulations, the incorporation of an accurate, distributed package model is very important to ensure sign-off quality results and to enable simultaneous chip-package co-design.