tag: power delivery networks

Managing Voltage Variation
By Barry Pangrle - 07 Aug, 2023 - Comments: 0

Engineers make many tradeoffs when designing SoC’s to better meet design specifications. Power, Performance and Area (PPA) are the primary goals and all three impact the cost of the implementation. For example, higher power and performance can both require more expensive packaging for power and signal integrity as well as cooling. The larger the die area the fewer die per wafer which drives u... » read more

Design Considerations For Ultra-High Current Power Delivery Networks
By Quaid Joher Furniturewala - 11 Jul, 2023 - Comments: 0

This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ. A power-delivery network (PDN), also called a power-distribution network, is a localized network that delivers power from voltage-regulator modules (VRMs) throughout a load board to the package’s chip pads or wafer’s die pads. The PDN includes the VRM itself, all bulk and localized capacitance, board vi... » read more

Distribution Of Currents In Via Arrays
By Siemens EDA - 24 May, 2023 - Comments: 0

It has become increasingly difficult in recent years to provide adequate PDNs on a PCB. The sheer number of different voltages, combined with increased current demands, makes distributing current around the board a substantial layout challenge. This paper demonstrates that by using appropriate and accurate simulations, combined with the improved intuition that such simulations bring, it is a ch... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm
By Ann Mutschler - 16 Nov, 2022 - Comments: 0

Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

Batteries Take Center Stage
By Heidi Elliott - 27 Dec, 2021 - Comments: 0

For any mobile electronic device, the biggest limiting factors are the size, age, type, and utilization of the batteries. Battery technology is improving on multiple fronts. The batteries themselves are becoming more efficient. They are storing more energy per unit of area, and work is underway to provide faster charging and to increase the percentage of that energy that can be used, as well... » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Reducing Power Delivery Overhead
By Brian Bailey - 08 Jul, 2021 - Comments: 0

The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

Auto Power Becoming Much More Complex
By Bryon Moyer - 14 May, 2020 - Comments: 0

Rising electronics content in automobiles is putting increased focus on automotive power delivery networks (PDNs). Safety implications mean that thorough power design and verification, along with novel power isolation techniques, are needed at the vehicle level, involving both electrical and mechanical considerations. The electronic takeover can be measured by the percentage that electronic ... » read more

Blog Review: Nov. 7
By Jesse Allen - 07 Nov, 2018 - Comments: 0

Arm's Shidhartha Das looks into maximizing the benefits of power delivery networks and explains a non-intrusive technique using an on-chip digital storage oscilloscope that can directly sample the power-rails to probe potential runtime bugs due to power delivery weaknesses. Synopsys' Snigdha Dua argues that scrambling is one of the most important features introduced in HDMI 2.0 and takes a l... » read more

Tech Talk: Power Sign-Off
By Ed Sperling - 06 Nov, 2014 - Comments: 0

Calvin Chow, area technical manager at Ansys, talks about power sign-off for complex SoCs at advanced nodes, including early stage prototyping, the importance of context, accurate power modeling of sub-blocks, and simulation of power-delivery networks. [youtube vid=MN4TjZ3dHVk] » read more

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