Productive Clock Domain Crossing Verification


Recently, we were invited to participate in an internal Chips@Cisco event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’s law with no slowdown any time soon.

Increasing SoC design size and complexity is no surprise to anyone, but what is exciting is that the latest FPGAs using the latest 3D technology can provide the same capacity as ASICs and accommodate multi-million gate designs including third-party IPs like SerDes, DSPs and CPUs. IP-based design methodology is becoming prevalent to not only manage the increasing complexity, but also to address time to market challenges. With an increasing use of IP, the number of asynchronous clock domains is increasing at a very rapid rate and has brought CDC verification to the forefront of the verification process. As with any other verification task, productivity to sign-off is very important for CDC verification.

FPGA users also will have to worry about CDC verification like their ASIC counterparts because of the complexity involved in assembly of third-party IP and hundreds of asynchronous clock domains.

Figure 1: Ingredients of a Strong CDC Methodology

Here are the important ingredients of productive CDC verification for both ASICs and FPGAs:

  • Easy Setup: SoC and IP teams define timing constraints in the Synopsys Design Constraints (SDC) format. CDC verification enabled by the use of existing constraints saves lots of time and effort.
  • Completeness of Checks: CDC verification needs to have a comprehensive set of asynchronous clock and reset checks. Verification experts should have the flexibility to add / remove checks, but a quality RTL sign-off solution should be available out-of-the-box. This eliminates the risk of missing critical CDC issues.
  • Easy Debug: CDC verification results should be presented in an intuitive way. To be productive with CDC verification, a designer should be able to easily figure out critical issues that he/she needs to fix.
  • Low Noise (false alarms): CDC verification should be able to understand the design intent and produce the results with high signal to noise ratio. Designers should not be required to waive violations for known design practices. This can be achieved by protocol independent CDC analysis, which means the solution should not completely depend on pre-defined design architectures.
  • Hierarchical Flow: IP-based design methodology requires designers to verify CDC at the IP level and then let SoC integrators perform verification at the chip level without having to worry about the internals of the blocks.

In addition to these key ingredients, a proven methodology is an integral part of productive CDC verification. SoC designers may not be deploying all aspects of the methodology today but it is important to understand that these avenues are available to address the productivity needs of CDC verification.

There are various CDC verification solutions available in the market. One has to look at these important ingredients and a proven methodology to pick the most productive solution to enable design teams to manage the complexity and the time to market challenges for both ASICs and FPGAs.


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