Special Report
Established Nodes Getting New Attention
Work is under way to improve energy efficiency and boost performance without relying on multi-patterning or finFETs.
Top Stories
IP Reaches Back To Established Nodes
As SoC developers shift backward to established nodes, steps can be taken to improve the IP’s functionality.
When Will 2.5D Cut Costs?
Stacked die appear inevitable, but at there is a lot of discussion about when they will offer economic benefits and what will drive a new cost equation.
Making Software Better
After years of warnings that software developers weren’t worrying about power, it’s time to step back and re-assess. Are we making progress?
Changing The IP Supplier Paradigm
Experts at the table: As the industry migrates from small blocks to larger integrated blocks and subsystems, it is having an impact on IP companies.
Test Becomes Power-Aware
Some of the same verification techniques apply, but it’s more complicated than that and errors can creep in where there are gaps.
Video
Tech Talk: Near Threshold Computing
First of two parts: ARM Fellow Rob Aitken digs into a technique that can increase power savings by 4X to 6X at established nodes.
Blogs
Editor in Chief Ed Sperling contends that the increased emphasis on squeezing more power and performance out of established nodes will only help when it comes to stacking them, in Improving 2.5D Components.
Executive Editor Ann Mutschler observes that breaking a complex problem down into more manageable pieces can make finding a solution much easier…even when it comes to power-aware test plans, in Partitioning The Problem.
Synopsys’ Mary Ann White takes a deep dive into Power Reduction Techniques. But are they the same for established planar, FD-SOI and finFET transistors?
Cadence’s Brian Fuller says all the usual business advice went out the window when semiconductor value chain shifted in If It Ain’t Broke, Start Fixing It Right Away.
Mentor Graphics’ Rizwan Farooq asserts that power needs to be optimized at the hardware and software levels, which only can be done by simulating an SoC and running the complete software stack, in The Revolution Will Not Be Televised: It Will Be On Your Phone.
Ansys-Apache’s Muhammad Zakir finds that finFETs are forcing a distinction between using a sign-off tool throughout the design flow versus signing off at the end of a design, in Changing The Meaning Of Sign-Off.
Atrenta’s Larry Vivolo examines how to empower assertion-based verification through automation in IP/SoC Verification With Assertions.
Rambus’Loren Shalinsky provides insights into how you can get a 40% reduction in power and a 5X capacity increase in Server Memory: Should We Be Concerned About The Power?
ARM’s Brian Jeff notes that designers need readily available and flexible IP that they can mix and match — especially in the smartphone and mobile computing arena — in Enabling The Next Mobile Computing Revolution.
Calypto’s Rob Eccles says there are a number of techniques for low-power design with different use cases for each — fine-grain techniques are useful for nearly all designs whereas coarse-grain techniques can be very effective for certain designs — in Creating A Strategy For Power Reduction In ICs.
