IP Reaches Back To Established Nodes

As SoC developers shift backward to established nodes, steps can be taken to improve the IP’s functionality.


Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality.

IP certainly can be improved to work faster at older geometries, stressed Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact. IP area also can be traded off for performance. Techniques range from layout design optimizations, like using larger channel transistors, to architectural duplication of functional units.”

Navraj Nandra, senior director of marketing for the DesignWare Analog and MSIP Solutions Group at Synopsys, agreed. He pointed out that while Synopsys is really focused on the most advanced nodes, which are used for graphics and application processors, that’s not the whole picture. “If you look at the foundry revenues, they are still making quite a lot of revenue out of nodes which are 55nm and bigger, so it would make sense if you want to consider a business around IP to look at those nodes,” he said.

Older technology nodes generally are less expensive from a design and manufacturing standpoint. Moreover, leakage really only began surfacing at 65nm, with issues showing up at 40/45nm that required extensive planning and automation. “IP providers are standardizing on functionality, yet offering the ability to be manufactured in different technology nodes,” said Arvind Shanmugavel, senior director, applications engineering at Apache Design. “Newer architectures with better efficiency can still be manufactured on older technology nodes, but at a lower cost with better standby leakage power. Mature technology nodes also give foundries the leverage to tune them for optimal performance.”

And from a device-level perspective, for any kind of analog-type performance, established nodes are actually better, Nandra said. “The devices are more linear, they have a better upward impedance, which means that you can do better designed analog precision blocks. The voltages are higher, which means the voltage headroom is bigger and the leakage is lower. So there are definite advantages in the more established nodes. There are also some drawbacks as we’ve seen because we’ve obviously been working on finFET technology and now we’re working on the next generation of finFET, so there have been some drawbacks with the larger nodes because the transistors are slower with the more established nodes, which means you have lower speeds, lower gain, lower maximum frequencies.”

For building blocks such as memory compilers and logic libraries, Synopsys has been able to innovate on the architectures for memory compilers, he continued. “We’ve got better high-speed, single-port register file compilers. We’ve got high-speed, dual-port-type designs built in leading-edge technologies.”

The advantage is that these can be ported backward to the more established nodes and the new architectures built on the latest technology generations can be applied to the more established nodes, he explained. Benefits include: better power consumption, better read and write assist technologies, lower leakage. “Customers have asked us to take those designs and back-port them to 28nm, to 55nm, or even higher. That’s something new we’re seeing. A lot of this being driven by IoT/wearable activity. Lots of companies are looking at building chips into wearable devices, but these must be really low-cost. And if they are low-cost they have to be in more established nodes like 55nm and bigger. But they also want the advantages that we’ve developed for the leading-edge nodes, and architecturally we can back-port this — and that’s what we’ve done.”

Achieving optimal performance
As IPs shift back to more mature nodes, it’s not always a matter of IPs needing to be improved to function faster. For most IP, the protocol defines a fixed performance, so going faster doesn’t buy anything, asserted Kevin Yee, product marketing director for the IP Group at Cadence. “The question is, really, why are some companies going back to more mature nodes (not really older nodes)? Mature nodes can be cost-effective and offer value such as low leakage for IoT applications, which is desired for low power applications. IPs can certainly be optimized and improved for these mature nodes and applications.”

However, technology has matured, and the ability to manipulate threshold voltages with techniques such as forward biasing to selectively speed up critical portions of a design provides the ability to achieve performances that were marginal in the past for certain IPs, he explained. More importantly, IPs have been optimized today to take advantage of the more mature process nodes — not just to achieve performance metrics, but to make tradeoffs to achieve optimal PPA metrics.

Riding the semi roadmap
Over the last decade, the business model has largely been based on riding the semiconductor roadmap to gain higher performance, lower power, and lower cost devices at each successive technology node. This meant adopting new technology nodes as quickly as possible, observed Mark Milligan, vice president of marketing at Calypto.

“However, the tremendous time to market pressures coupled with high implementation costs, including IP qualification and timing closure at that new node, meant that design teams were focused on IP integration and RTL verification tasks. In some cases there was little time for architecture or microarchitecture exploration. Teams had to rely on their experience and expertise to make a judgment call, then implement it. Now, the benefit of sticking with older nodes means lots of IP blocks have been qualified, the EDA tool flow is robust, and you know how to get timing closure. Plus, you can ride the yield curve to help with device cost. This affords the opportunity to pick those key IP where you want to differentiate and thoroughly try out multiple architectures to tune it to your customers’ requirements,” he concluded.

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