The Revolution Will Not Be Televised: It Will Be On Your Phone

Power needs to be optimized at the hardware and software levels, which only can be done by simulating an SoC and running the complete software stack.


The advent of smart devices has ushered in a revolution all over the world. The most widely used smart device is the mobile phone, which has radically changed the way we communicate. There are many other types of devices running 24/7 in our homes, hospitals, businesses, etc. No matter what kind of functionality smart devices have, they have one thing in common: they all consume energy.

They also contain embedded processors that run some type of firmware and an operating system that gives it life; both of these come at a higher energy cost. We are always looking to hook up our mobile devices to an outlet and the battery manufacturers have their own laundry list of problems to pack more power into smaller packages. The software applications running on these devices cause more circuits to switch and hence lead to more power consumption.

The power needs to be optimized both at the hardware level and at the software level, which can be achieved only by simulating an SoC running the complete SW stack. Today’s SoCs are being designed for minimizing the use of power at the hardware level using techniques like switching off power to the circuits that are not in use; for example,, shutting off the LCD screen during a call or shutting off the Bluetooth antenna in the absence of connected devices. This requires SW controlled circuits that can power ON/OFF parts of an SoC’s circuits.


All this has added multi-dimensions of complexity in verification at all levels of design — from the blocks to the SoC to the application SW. In order to meet already shortened design cycles, a new generation of verification tools is necessary to make your projects successful in today’s market. Mentor offers a complete suite of design tools to help you design your next SoC, complete with embedded SW. Verification at the SoC level requires running long test and billions of cycles to boot the OS, running some application to verify the HW and SW together. Emulation tools speed up the OS booting process to shorten the verification cycle, and features offered by Mentor Graphics Veloce, such as replay, can eliminate the need to re-run tests. The deterministic nature of replaying a recorded test run gives the user the ability to play back and quickly capture bug causing sequences. You can also use the Veloce Power Aware Verification flow to test power management features implemented in the SW and HW. Emulation solutions like these allow you to run real-world tests in a targeted application environment, so you won’t be left behind when the revolution’s here.


[…] Graphics’ Rizwan Farooq asserts that power needs to be optimized at the hardware and software levels, which only can be […]

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