Creating A Strategy For Power Reduction In ICs

There are a number of techniques for low-power design with different use cases for each. Fine-grain techniques are useful for nearly all designs whereas coarse-grain techniques can be very effective for certain designs.


In last month’s blog, various power saving techniques were presented. These different techniques fit into three categories: gross (or coarse-grain) design, fine-grain design, and fine-grain process.


In this blog, different techniques will be compared. By understanding the different techniques, it will become clear which ones to use in your design.

Fine-grain process techniques
For the different process techniques, there are costs and benefits. In general, the tradeoff is between speed and power.

The multi-Vth (multiple threshold voltage) approach is a logic synthesis technique where the synthesis tool and/or the static timing analysis tool are allowed to determine the optimal Vth of each logic cell in order to meet the timing requirements for a path with minimal power. The synthesis tool is presented with multiple standard cell libraries, functionally identical, but with different Vth transistors used. The tool will select the lowest Vth required in order to meet timing requirements.

Back biasing is a technique that will reduce leakage power. It works by changing the substrate voltage(s) of the transistors in the design and thereby reducing capacitance. The cost is an increase in design complexity by implementing the bias voltage. This technique may not be applicable to processes with insulating substrates.

Low power processes have been optimized for lower power. They generally trade off some performance in order to achieve lower power.

Fine-grain design techniques
For fine-grain design techniques, the tradeoffs are between power savings and an increase of area or delay. A key advantage to fine-grain techniques is that they can be done automatically with tools.

Clock gating is frequently used to reduce power in logic designs. The idea is to identify situations where the data input of a flip-flop can be safely ignored. When the input can be ignored, the clock can be removed (gated) for that cycle. There is an overhead to doing this; additional logic is required. The tradeoff is to determine if the power saved by gating is greater than the power used by any added logic.

Memory gating is very similar to clock gating. In this case there are more inputs to be considered (address, write enable, data, light sleep), but the process is similar. There is the power saving tradeoff, and in this case more logic can be accepted because the power savings are greater than for registers. Memories often have power saving modes: shutdown, light sleep, and heavy sleep. Invoking a power saving mode is very effective. Light sleep support can be added automatically. Other modes may require an architectural change.

Still another fine-grain technique is data gating. Here we are not gating a storage element, but rather a block of combinatorial logic, such as an adder or multiplier.

All of these fine-grain techniques are best done with the help of a software tool: enable logic expressions can be numerous, very complex, and time-consuming to implement and test.

Coarse-grain design techniques
Gross (or coarse-grain) techniques are done at a higher level. These have more overhead and are controlling the power to significant amounts of logic.

Power gating refers to powering down entire blocks of logic. Blocks are powered off completely. This kind of technique requires careful consideration of the ramifications. Unlike fine-grain techniques, which can be applied everywhere automatically, power gating must be applied judiciously by the designer. The logic to implement the power on/off signal is likely to be controlled by software. Retention flops or external memory can be used to preserve the logic states of flip-flops in the powered down block.

Dynamic voltage and frequency scaling (DVFS) is a technique that adjusts frequency and voltage dynamically to trade off power and performance. This is appropriate for SoC designs with a high and a low performance setting. This technique can be very effective, however there is a significant effort required to design and verify this solution.

There are a number of different techniques for low-power design. Fine-grain techniques are useful for nearly all designs. Coarse-grain techniques can be very effective for certain designs.

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