Are We Headed For A Power Wall?

A common theme in semiconductor design circles today are the many power reduction techniques available to engineers to bring the power down in their devices. While power gating and other techniques are effective today, it does lead to questions about how long they will continue providing a benefit. Anand Iyer, director of product marketing for [getentity id="22016" e_name="Calypto"], believe... » read more

Datacenter Power Is Different

With much focus on super low power devices for handhelds and IoT applications, I’m also interested in what’s happening at the seeming other end of the spectrum, in the datacenter. Atrenta CTO Bernard Murphy rightly pointed out that when it comes to power reduction techniques, datacenter power is a different story. He reminded that at a unit-level, a lot has already been done or is underw... » read more

Creating A Strategy For Power Reduction In ICs

In last month’s blog, various power saving techniques were presented. These different techniques fit into three categories: gross (or coarse-grain) design, fine-grain design, and fine-grain process. In this blog, different techniques will be compared. By understanding the different techniques, it will become clear which ones to use in your design. Fine-grain process techniques For ... » read more