Special Report
Crisis Ahead: Power Consumption In AI Data Centers
Four key areas where chips can help manage AI’s insatiable power consumption.
Top Stories
Re-Architecting AI For Power
Is AI using too much power? Some people think so, and believe the easy gains in power reduction have already been made.
Reliable Training Data Paramount To AI Model Success
It’s not enough to have a data lake. It must be trustworthy, reliable, and protected.
Will New Processor Architectures Raise Energy Efficiency?
New approaches are needed as current processors run out of steam.
Can Cheaper Lasers Handle Short Distances?
VCSELs may serve in more non-photonic applications.
Chiplet Ecosystem Slowly Emerges
Before the transition can be made from custom chiplet environments to a standardized off-the-shelf open marketplace, an ecosystem must be created.
When Standards Enable Chiplets
Nobody wants standards until the lack of them inhibits the development of the solutions that they need. That is often too late.
Video
Workload-Specific Hardware Accelerators
What differentiates accelerators from other processing elements.
What’s Different About HBM4
New DRAM standard aims to solve a critical bottleneck.
Opinion
Is There Still a Future for Hard Disk Drives?
The cost of HDDs and SSDs will continue to fall, while capacity will continue to increase in both.
Sponsor Blogs
Synopsys’ Madhumita Sanyal and Diwakar Kumaraswamy explain why real-time inference and large-scale training are pushing the limits of interconnect performance, in System-Level Design For 1.6 Tbps Interoperability In AI Data Centers.
Siemens’ Shivani Joshi finds that adaptive optimization algorithms can deliver better results and deeper insight into why certain designs perform better than others, in Moving Past “It Works” — Intelligent Optimization Is the Key to PCB Excellence.
Rambus’ Raj Uppala shows how a single memory failure in a hyperscale AI cluster can cascade into hours of lost compute time, in Maximize Uptime And Improve TCO: RAS And Telemetry In HBM4 For Data Centers.
Cadence’s Harinee Rathod looks at a fine-grained and efficient control flow that ensures lossless packet delivery, in UEC-CBFC: Credit-Based Flow Control For Next-Gen Ethernet In AI And HPC.
Ansys’ Jayraj Nair examines how multi-physics simulation enables designers to explore novel architectures that would otherwise be too risky to attempt, in Digital Engineering Transforms Chips For The Future.
Arm’s Sergio Alapont Granero explores how to get desktop-class visual fidelity in mobile gaming with dedicated neural accelerators, in Start Experimenting With Neural Super Sampling For Mobile Graphics.
Sponsor White Papers
Scaling DRAM Technology To Meet Future Demands: Challenges And Opportunities
A tutorial on DRAM architecture, specifically looking at design tradeoffs and subsequent impact to the overall system performance, power, cost and reliability.
Building An AI Chip: Pre Silicon Planning
The importance of early architecture exploration to avoid costly design revisions and ensure optimal power-performance trade-offs.
AI and Data-Driven Methods To Make Telecom Networks Smarter, More Efficient
Networks are getting faster. Planning them should be smarter.
Edge AI: Enabling Smart IoT Applications
Practical applications, implementation strategies, and the platform technologies enabling scalable, intelligent edge AI solutions.
Best Practices to Optimize Infrastructure for Simulations
Accelerate product design and delivery by empowering next-level digital engineering with secure, reliable high performance compute infrastructure.
Time-of-Flight Decoding Enhanced By Tensilica Vision DSPs
How DSP architecture is significantly advancing ToF decoding, achieving substantial performance gains over conventional methods.
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