Scaling DRAM Technology To Meet Future Demands: Challenges And Opportunities

Since the invention of the 1T1C bit cell more than 50 years ago, DRAMs have become the main memory of choice for processors in computer systems and many consumer electronics devices. As new use computing paradigms have been created, including 3D graphics, cloud computing, smart phones, and AI processing, specialized processors and DRAM memories have been developed that are optimized for these use cases. The same 1T1C DRAM bit cell is used in each of these applications, but the internal architecture and interfaces of the DRAMs supporting these markets are optimized in different ways, and the DRAMs are packaged differently to meet the needs of the system.

Across all markets, there is a relentless demand for higher performance and better power efficiency, as DRAM bandwidth can bottleneck application performance and interfaces to DRAMs can consume half of the SOC power. DRAMs are also being stressed by growing reliability concerns as they incorporate on-die ECC and mitigation for disturbance effects such as RowHammer and RowPress. As the momentum of AI continues to grow across markets (HPC, server, client, mobile, etc.), the design of efficient, performant and reliable memory systems is becoming increasingly critical. AI models are continuing to grow, pushing the capacity and bandwidth requirements of DRAMs. Simply scaling with historical techniques will no longer achieve the required characteristics due to physical challenges, limits of process scaling and system architecture constraints including thermals and power delivery.

This tutorial will describe DRAM architecture in detail, covering the similarities and differences between different DRAM technologies. Standard scaling techniques will be highlighted along with challenges that the industry is currently facing. Input from industry experts will show the pros and cons of DRAM architecture choices, demonstrating the system impact and requirements for mainstream adoption. Future DRAM architectures will also be discussed.

Read more here.  Presentation at the 2025 International Symposium on Computer Architecture (ISCA) at Waseda University in Tokyo by Steven Woo and Wendy Elsasser from Rambus and Taeksang Song, Samsung Electronics.

Fig.1: The Evolving Compute Memory Hierarchy. Source: ISCA ’25 Tutorial: Scaling DRAM Technology to Meet Future Demands – Challenges & Opportunities.