Special Report
Noise: A Chip Killer
Concern is growing in complex designs where there are few dedicated tools to help find and deal with it.
Top Stories
Power Integrity And Voltage Issues Get Harder To Detect And Solve
Inconsistent demand from multiple features can greatly increase the number of corner cases.
Multiple AI Scale-Up Options Emerge
As data center infrastructures adapt to evolving workloads, parts of Ethernet can be found in scale-up approaches.
Video
Critical Factors For Storing Data In DRAM
New concerns and challenges for memory in AI data centers.
LPDDR6: Not Just For Mobile Anymore
Why and how the go-to-DRAM for low-power devices is pushing beyond its roots.
Sponsor Blogs
Fraunhofer IIS/EAS’ Roland Jancke looks at balancing the benefits provided by community and transparency with the risks posed by capacity and warranty issues, in Opportunities And Challenges With Open-Source Hardware In System Development.
Rambus’ Lou Ternullo discusses signal quality across long distances and complex topologies, in Scaling AI Infrastructure: The Critical Role Of PCIe 7.0 Retimers.
Siemens’ Farhad Ahmed examines an effort to shift verification from a single, time-consuming flat run to a more efficient, distributed, and scalable process, in Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis.
Synopsys’ James Chuang explains how to compress multiple design scenarios into manageable sets while preserving critical timing information, in Predictable Design Optimization And Closure With Adaptive Scenario Compression.
Arm’s Martin Weidmann details how upcoming features will extend the ability to detect memory safety violations to more systems and provide application component isolation within a single process, in Future Architecture Technologies: POE2 And vMTE.
Cadence’s Kunal Chhabriya shows how L1 link substates and PHY PIPE states provide granular control over power consumption, in PCIe Low-Power Validation Challenges And Potential Solutions.
Ansys’ Laura Carter distills information executives shared during a recent event on the early integration of AI, data, models, and simulations, and their impact on design decisions, in The Future Of Digital Engineering In The Age Of AI.
Siemens’ Amr Hegazy, Mohamed Abdelkarim, and Reem El Adawi break down a new approach that enhances AI understanding through hierarchical clustering techniques with LLM-driven keyphrase extraction, in Unlocking Clarity: Keyphrase Trees Bring Structure To AI Text Analysis.
Sponsor White Papers
High Bandwidth Memory (HBM): Everything You Need To Know
How HBM works, how it compares to previous generations, and why it’s becoming the cornerstone of next-generation computing.
Standardization Of HDMs For Hierarchical CDC And RDC Analysis
New Accellera working group is developing a way to run hierarchical data models on any vendor’s tools without exposing third-party IP.
A Guide To Accelerating Your Design Timeline With Electromagnetic Analysis
How to choose the right electromagnetic (EM) solver—from 2D and hybrid methods to full 3D FEM.
Why Arm For Cloud: At A Glance
Arm Neoverse enables leading cloud performance and cost efficiency with AWS Graviton4.
Navigating Vehicle Engineering In A Software-Defined World: Ebook
The components that make SDVs possible, from applications and operating systems to middleware that ensures seamless integration between hardware and software.
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