Noise: A Chip Killer

Noise has always been important to communications experts, but it’s quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised.

Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intended time, or for the voltage at a device to remain constant enough to be able to reliably create or sense a signal.

In the communications space, noise is usually analyzed using eye diagrams. These diagrammatically show if the noise encroaches into the region defined for reliable signal extraction. Noise is in two dimensions — amplitude and phase. Phase noise comes about because of changes in timing on signals, particularly clocks. Amplitude noise also can impact timing by causing clock edges to move out of phase (jitter).

Noise injection comes from many sources. At the device level, it starts with bias-temperature instability and flicker noise, but the noise sources that are of growing concern are orders of magnitude larger in terms of their ability to compromise larger portions of a design.

“As semiconductor technology scales below 7nm and packaging becomes more complex, power delivery noise has become a major challenge,” says Muhammad Hassan, 3D-IC solutions engineer at Siemens EDA. “Lower supply voltages, higher current densities, and denser interconnects increase IR drop, inductive noise (L·di/dt), and power distribution network (PDN) discontinuities across stacked dies. If not properly managed, dynamic voltage noise can reach 5% to 10% of the nominal VDD.”

Managing noise has become one of the most critical and persistent challenges in modern semiconductor design. “With supply voltages shrinking toward 1 volt and transistor densities continuing to increase, traditional design margins that once absorbed electrical variations are all but gone,” says Charlene Wan, vice president of branding, marketing, and investor relations at Ambiq. “Even minor fluctuations that were once inconsequential can now jeopardize performance or reliability.”

Power and signal integrity
In some cases, the problems are not new, but the context around them has changed. “Signal integrity has been done on the system side for over 30 years,” says John Park, product management group director in the Custom IC & PCB Group at Cadence. “We have advanced three-dimensional electromagnetic field solvers that are going to extract very accurate S parameters of a channel, and allow you to model that. However, if you are a die designer, that whole concept may be new, unless you do analog. There is a convergence of what we historically did on the die side and what we’ve historically done on the system side.”

Leading-edge chips today are consuming vast amounts of power, and that is creating problems. “Noise is an analog layer on top of digital designs,” says Marc Swinnen, director of product marketing at Ansys, part of Synopsys. “The power line is meant to be perfectly stable, but it isn’t, and that is power noise. Digital blocks often have intense bursts of action that impact the power supply. For analog designs, or more sensitive regions of digital designs, you need the power to be more stable, so they have separate power lines.”

This creates other problems. “Currently, in a complex SoC, you have 20 or 30 voltage domains, but only 2 or 3 of them are high current domains,” says Andy Heinig, head of department for efficient electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “There is the core voltage, and maybe 1 or 2 I/O voltages with high currents. Then you have 10 or 20 voltage domains that consume microAmps, only used to standardize something, such as a PLL. You have to reduce the noise on these to the lowest level. But with advanced packaging, we bring all the interconnects much closer to each other, and we get more crosstalk. The problem is not the absolute level of the noise. It is that we have more noise on all the supply nets, including the critical ones. We can’t avoid that as we get them closer to each other. In total, more noise, more coupling, and that can introduce new problems.”

Some of these problems are becoming more apparent with advanced packaging. “In analog and mixed-signal designs, such as DDR PHYs or HBM memory interfaces, IR drop can have particularly severe consequences,” says Takeo Tomine, principal product manager at Ansys, part of Synopsys. “For example, in a DDR interface, localized IR drop in termination or driver circuitry can degrade signal swing, resulting in eye closure and bit errors. Similarly, in HBM designs, where multiple high-speed I/O channels operate in parallel, even minor voltage dips can disrupt timing margins and cause data corruption or synchronization failures.”

Other system problems are also migrating inside the package. “When you have a system with multiple elements on it, such as the case with a PCB, and if you have one chip being active, then a different chip being active, then back to the first, you can get power oscillations build-up,” says Ansys’ Swinnen. “There are resonant frequencies in the power distribution network, and if you draw power at the right frequencies, you can get these oscillations that build. These are low-frequency oscillations. This did not happen with monolithic devices.”

These issues become more challenging as package sizes grow. “When you start getting into interposers with long traces off to other die, L’s can very much become an issue,” says Joe Davis, senior director of product management at Siemens Digital Industries Software. “You do have resonances. You start to have the same signal integrity issues in a 3D-IC that you have with a traditional package. Because you’re talking about shorter things, shorter traces than wires, it’s less of an impact. But these things are getting so large today, when you look at the roadmaps for the foundries and the systems that they’re planning to put together with hundreds of dies, L’s and C’s become a significant impact.”

It is not just data center designs that are impacted. “For ultra-low power chips operating near threshold voltage, such as those designed for wearables and IoT edge devices, the problem is magnified,” says Ambiq’s Wan. “These SoCs trade voltage margin for energy efficiency, which means they are inherently more susceptible to droop, jitter, and crosstalk.”

Multi-physics world
Multi-physics problems are becoming commonplace. “From a packaging perspective, advanced platforms such as 2.5D/3D integration, fan-out, and redistribution line interposers introduce new challenges,” says Rozalia Beica, field CTO for packaging technologies at Rapidus Design Solutions. “Analog blocks are vulnerable to power integrity issues, thermal gradients, and inter-die crosstalk, all of which can degrade performance. System-in-package (SiP) designs combine RF, analog, and digital components, which further complicates verification, requiring multi-physics simulations that account for electromagnetic interference, thermal behavior, and signal integrity.”

What is new are some of the electromagnetic coupling problems. “Digital systems have interesting noise problems,” says Nilesh Kamdar, general manager, design and verification business unit at Keysight Technologies. “They are really easy noise problems compared to microwave or RF systems. As you go higher and higher in frequencies, everything is noise. Everything is either impacting you positively or negatively, but the high-frequency problem means a small piece of package, a small piece of connection, can be an antenna. It can leak signals from that if not properly designed and impact the chip next to the first one.”

This should not have come as a surprise. Mo Faisal, Movellus’ CEO, predicted this seven years ago when he said, “You can take a chip and put a wire on top of it – literally on top of it – and hook that up to a scope and you will see noise at the frequency aligned with what it is switching at. If a wire can detect it, then so can a 3D die stack. This is a system-level concern, and you have to find ways to spread that noise and not have everything stacked up at the same frequency. There will be EM radiation that will go from one device to the other. This is where system techniques such as spread spectrum come into play and allow you to spread out the noise so that it does not interfere.”

Additional problems are only just becoming better understood. “You cannot take a 5G-, 6G-type of complex chip or packaged system and assume that it will work based on past experience,” says Keysight’s Kamdar. “Now we are getting into the world of multi-physics problems. Electromagnetic effects are one problem. Power leakage can be another problem. Thermal effects are another problem. The interesting thing is that all three of these interact with each other. There are problems where, at higher temperatures, the electromagnetics change — or the impact of that higher power causes a thermal impact. All of these things work against you. Now you’re trying to analyze a multi-physics problem that you previously could ignore because systems were far enough away and weren’t really interacting that much. Now you absolutely have to handle them. This is a brave new world for us, where everything is multi-physics. As we go to denser technologies, like chiplets, and higher frequencies, like millimeter wave, we have to manage this in a different way.”

Some new effects are impacting existing problems. “As customers are pushing the frequency higher, they want to have better modeling for their clock jitter and clock uncertainty,” says Manoz Palaparthi, senior staff product manager at Synopsys. “These are effects that have always been present in the design, and customers add some margins to counter these effects. But now, aging has become a concern, and people need to know both the fresh clock jitter and the aged clock jitter. Two years down the road, how does my clock structure behave? Is there more distortion of the duty cycle, or does the jitter vary?”

Analysis
Noise is placing an increasing burden on verification. “Circuits, such as HBM, bring together deeply intertwined analog and digital domains, making verification both broader in scope and more mission critical,” says Karthik Koneru, principal product manager at Synopsys. “Regression suites now encompass thousands of tests, requiring not just functional correctness, but also high accuracy across process corners, noise conditions, and timing scenarios. The challenge is acute. You need the precision of analog verification without compromising the speed required for digital-scale regression.”

The impact is real, too. “SoCs with AMS content typically have first-time success rates 10% to 15% lower than their digital-only counterparts,” says Rapidus’ Beica. “This gap is often due to insufficient corner-case coverage, inadequate modeling, or integration issues like power domain conflicts and substrate noise.”

Analysis methodologies can combine static and dynamic IR drop simulations, electrothermal PDN modeling, and on-die voltage sensors to capture transient drops and resonant behavior across frequency ranges. “Mitigating noise and its impact can be done at the silicon, package, or board level,” says Siemens’ Hassan. “At the silicon level, wider power rails, more vias, decoupling capacitors, as well as global optimization strategies such as current-aware floor planning and adaptive voltage scaling can be employed. At the package or board level, designers can utilize hierarchical decoupling (die, package, PCB), low-inductance power/ground planes, optimized PDN impedance, and placement of high-efficiency VRMs near the load.”

Model verification has become much more important. “I see a lot of time and effort being spent on model verification, and if it is not done, then your entire foundation is wrong,” says Sathish Balasubramanian, head of product management and marketing for AMS at Siemens. “And in your verification, you suddenly see that the PLL has a lot more clock jitter, or your PLL is not really coming up with the clock that you wanted. There’s quite a bit of nuance going on there. Model verification has become a big pain point.”

Perhaps the biggest issue is that many noise failures fall into the category of silent data errors, where the root cause cannot be identified and is extremely difficult to reproduce. “In low-power devices, these failures may not manifest as a system crash,” says Wan. “Instead, they may be seen as reliability drift, a sensor miscount, a missed Bluetooth packet, or excess current draw leading to reduced battery life.”

Impacts on teams
These are not just technical problems. They present organizational challenges, as well. “We need a new understanding about how much noise can be accepted,” says Fraunhofer’s Heinig. “With chiplets and advanced packaging, we will get more questions. On the power side, we need more simulation to avoid IR drops, especially under different workloads. This is a big problem, because if we integrate everything closer to each other, we start to see problems with overlapping domains. Engineers separate everything into domains. We had the power domain. The power domain has its own models, and they are able to solve those problems. Now we bring everything closer to each other, and we have much more interaction. It means the engineers have to work together, but they are not talking the same language.”

Everyone has to learn new skills. “As a digital IC designer, never in the past did I think I needed 3D electromagnetic solver to figure out what’s going on,” says Cadence’s Park. “Now you do. I’m a package designer. I never knew I needed to do formal DRC. Well, now you do. It is the convergence of system design tools and expertise, and die design tools and expertise. We’re talking digital, obviously, on the analog or RF side of things. They’re very familiar with electromagnetics. A lot of what we focus on is how we integrate these flows so you don’t have to jump over a 10-foot wall to get in between these tools that you need to use in the flow.”

Possible solutions
Noise can be managed using existing tools. “At the front end, we can influence noise indirectly through RTL design choices, such as activity balancing, clock gating, and power domain control,” says William Wang, CEO of ChipAgents. “But the real leverage for minimizing IR drop and power integrity noise lies in the back end, where power grid design, decoupling strategies, and package layout determine the actual noise behavior. Looking ahead, AI agents could play a major role in backend optimization by autonomously analyzing EM/IR simulations, learning from past sign-off data, and suggesting layout or decap placement improvements to reduce droop hotspots and optimize power distribution efficiency across chip and package levels.”

As problems get worse, more time and effort is spent on looking at long-term solutions. One area under consideration is increased adoption of on-chip voltage regulators. “The bottleneck for integrated voltage regulators is developing the magnetics that will allow you to integrate those magnetic components inside the package,” says Luca Vassalli, customer applications engineering director at Empower Semiconductor. “A switching regulator needs inductors to operate efficiently, and those inductors need to store energy and be as efficient as possible so they do not dissipate too much power. To make them small, you have to increase the switching frequency of the converter and still maintain very high efficiency despite the smaller size.”

There are downsides. “It means additional area, and that means additional cost,” says Heinig. “And it isn’t necessary yet, because you have been able, by designing your package in the right way, to avoid the critical supplies from getting noise from other signals using separating and shielding. But by using an internal voltage regulator, maybe this avoids the complex simulation. Even if you bring in noisy signals on the supply, it is internally regulated, and you can be quite sure that your PLL, for example, gets a noiseless single net. Maybe this is a technical solution to avoid this complex simulation, because you solved it in a different way. The old way is to avoid noise on the supply. Now we have an internal filter that filters out the noise. But you only adopt new approaches if you really need to, because in the beginning, it brings uncertainties, and something else may go wrong.”

Unfortunately, it mainly comes down to tightening engineering disciplines. “No design can eliminate noise, but it can be mitigated through careful architecture and implementation,” says Wan. “Your mindset matters. Treating chip, package, and system as an integrated PDN design challenge will help build less noisy chips from the start. The trend toward heterogeneous integration, denser packaging, and near-threshold computing will only make noise noisier and more complex to manage. For ultra-low power systems, it’s extra weeks or months of battery life saved by keeping noise under control.”