Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis

The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It’s a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries.

Questa CDC and RDC solutions handle large designs by employing a hierarchical methodology built around the concept of a hierarchical data model (HDM). This approach shifts the verification effort from a single, time-consuming flat run to a more efficient, distributed, and scalable process.

What is the hierarchical flow?

In large-scale designs with numerous asynchronous clocks and resets, a traditional flat analysis of the entire system can take days to run and can be extremely difficult to debug. The hierarchical flow addresses this by:

1. Bottom-Up Verification: The design is broken down into smaller, manageable blocks or sub-systems (often IP blocks).
2. Block-Level Analysis: CDC and RDC analysis is performed on each block individually to ensure it is “clean” of internal domain crossing violations. This is faster and easier to debug at a lower level of complexity.
3. Abstraction and Modeling: Once a block is verified, its internal details are abstracted into a HDM or an abstract model. This model captures the block’s CDC/RDC-relevant information (like clock and reset paths and synchronization intent) without including all the internal RTL logic.
4. Top-Level Signoff: The HDMs of the sub-blocks are used at the higher levels of the design (sub-system and then full SoC) to perform the final signoff analysis. This greatly reduces the runtime and memory requirements by replacing millions of internal gates with an abstract model.

CDC and RDC hierarchical flow

Questa CDC and RDC hierarchical flow from Siemens EDA offers two methodologies. One is called bottom-up analysis, and the other is called top-down analysis. Project teams should use the methodology that best matches their project design flow.

In some IP-based SoC projects, block design and verification start before the top-level design and constraints are available, so a bottom-up flow is most effective, as shown in figure 1.

Fig. 1: Bottom-up hierarchical flow diagram.

In the bottom-up analysis method, first designers run CDC/RDC analysis for each block and then load the generated HDMs and run top-level CDC analysis. Typically, various IP teams analyze their blocks separately — so the integration team needs only the hierarchical databases when analyzing the top-level.

There are some prerequisites to run bottom-up analysis. Users need to ensure that the specified block instances do not have hierarchical references to objects in the top-level module or to other block instances, and vice versa. That is, when users analyze a hierarchical block, all of its hierarchical references must be resolved to objects that are not in any of the analyzed blocks.

On the other hand, some projects start CDC/RDC analysis after top-level design and constraints are available, so a top-down flow is most effective, as shown in figure 2.

Fig. 2: Top-down hierarchical flow diagram.

In the top-down analysis method, top-level constraints are used on the full chip design to run CDC or RDC analysis. The Questa tool automatically infers the block-level constraints for each hierarchical block and runs analysis on each block. It generates HDMs for each block. Users then use the HDMs to run top level analysis. Prerequisites to run a top-down method are similar to bottom-up method described above.

Questa CDC and RDC hierarchical flows support multiple HDM formats, white-box, black-box, and user-defined Tcl-based formats. In white-box format, Questa creates binary outputs for each HDM model, which can be used when running top-level analysis. The advantage of this flow is that binary HDM can be used to see the internal schematic view of the HDM models. In black-box and Tcl-based formats, no schematic view is available to see the internals of the block designs.

Standardization of HDMs for hierarchical CDC and RDC analysis

Currently, Questa HDMs can be consumed only by Questa CDC and RDC tools. To resolve this problem, a working group was formed within the Accellera organization in January 2023 to explore the need for the creation of a standard to converge CDC and RDC collateral integration from different tools and vendors for ease (time-to-market) and quality (bug-free silicon). The Accellera board approved this working group and tasked it to develop a standard format that will be accepted by the semiconductor as well as EDA communities.

Fundamentally, what is being proposed is a common CDC interface standard that:

1. Every vendor/tool can translate their native format to/from (maintaining their IP)
2. Every IP vendor can run their tool-of-choice to verify and produce collateral and generate a standard format for SoCs that use different tools
3. Every SoC can quickly and safely integrate either native collateral or translate from the standard collateral into their tool-of-choice

The Accellera CDC Working Group goal, as approved by the Accellera board, is as follows:

1. Produce an LRM for publication by mid-2026
2. Support all EDA vendors in developing tools that meet this specification in generated collateral
3. Enable IP companies to generate collateral using various vendors and tools
4. Enable SoC companies to consume generated collateral from different vendors/tools into their tool-of-choice

Most leading semiconductor companies around the globe are participating in this initiative. Also, leading EDA vendors who provide tool solutions in CDC and RDC domains are actively involved, including Siemens EDA. Below is a partial list of the participating companies:

Table 1: Companies participating in CDC Working Group.

The most important motivation for the semiconductor design houses is that they don’t have to be dependent on one EDA vendor tool to do their CDC and RDC analysis. IP provided by IP vendors created with one particular EDA or IP tool can be used by another group using their tool of choice.

Since the inception, the working group participated in various conferences and gave presentations on the importance of defining a standard model. The figure below shows the list of the various conferences where CDC working group members gave presentations.

Fig. 3: Conferences where CDC Working Group gave presentations.

Members of the Siemens CDC-RDC product team have worked with the working group from the beginning. Siemens engineers provide suggestions for the attribute definitions and participate in various conferences as presentation speakers on behalf of the working group. Once the published LRM is available, Siemens R&D will review and commit to supporting the generation and consumption of these standard formats for running Questa CDC and RDC tools. Siemens strongly believes that a standard format for HDMs will benefit Siemens customers tremendously. They will be able to consume 3^rd-party IP and complete their CDC and RDC RTL analysis without any restrictions. Companies can support multiple EDA tools as PoR and as a second source, and they can use the same HDM on all their EDA tools for CDC and RDC analysis.

Hierarchical analysis helps enable analysis in parallel with teams across the globe. Even with all the significant progress in the capabilities of EDA tools, the major bottleneck in CDC-RDC analysis of complex SoCs and chiplets is consuming HDMs generated by different vendor tools. The initiative by Accellera CDC Working Group is a step in the right direction toward setting a standard format for HDM files.

For more on how hierarchical clock domain and reset domain crossing analysis allows parallelization of sub-block and noiseless analysis, reduces SoC runtimes, and speeds closure of CDC and RDC issues, and for more on the work of the Accellera CDC Working Group to support the use of multi-vendor tool flows, please read the new paper from Siemens, Standardization of HDMs for hierarchical CDC and RDC analysis.