tag: reset domain crossing

Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis
By Farhad Ahmed - 13 Nov, 2025 - Comments: 0

The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
By Reetika - 30 Oct, 2025 - Comments: 0

As system-on-chip (SoC) designs evolve, they aren’t just getting bigger — they’re becoming more intricate. One of the trickiest challenges in this evolution lies in handling resets. Today’s architectures often juggle multiple asynchronous reset sources alongside sequential elements such as non-resettable registers (NRRs), which operate without dedicated reset pins. When a signal crosses... » read more

Top Five Trends In RTL Signoff
By Suresh Babu Barla - 30 Oct, 2025 - Comments: 0

By Suresh Babu Barla and Rimpy Chugh The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage occurs far too late in the design development process. At this point, addressing such problems demands significant effort, primarily because most design-r... » read more

Addressing Reset Tree Design Challenges For Complex SoCs With Advanced Structural Checks
By Reetika - 12 Dec, 2024 - Comments: 0

As SoC designs continue to evolve, the complexity of reset architectures has grown significantly. Traditionally, clock tree synthesis has been a major focus due to timing challenges, but now reset trees demand equal attention. With multiple reset sources, designers must deal with reset trees that can be more intricate than clock trees. Errors within a reset tree can lead to serious issues, incl... » read more

Elimination Of Functional False Path During RDC Analysis
By Farhad Ahmed - 12 Sep, 2024 - Comments: 0

Reset domain crossing (RDC) issues can occur in sequential designs when the reset of a source register differs from the reset of a destination register, even if the data path is in the same clock domain. This can lead to asynchronous crossing paths and metastability at the destination register. RDC analysis on RTL designs is done to find such metastability issues in a design, which may occur du... » read more

Techniques To Identify Reset Metastability Due To Soft Resets
By Siemens EDA - 05 Jun, 2024 - Comments: 0

Modern SoCs are equipped with complex reset architectures to meet the requirements of high-speed interfaces with increased functionality. These complex reset architectures with multiple reset domains, ensure functional recovery from hardware failures and unexpected electronic faults. But the transmission of data across sequential elements that are reset by different asynchronous and soft reset ... » read more

Reset Domain Crossing Verification
By Reetika - 13 May, 2024 - Comments: 0

By Reetika and Sulabh Kumar Khare To meet low-power and high-performance requirements, system on chip (SoC) designs are equipped with several asynchronous and soft reset signals. These reset signals help to safeguard software and hardware functional safety as they can be asserted to speedily recover the system onboard to an initial state and clear any pending errors or events. By definiti... » read more

Accellera Preps New Standard For Clock-Domain Crossing
By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

Formal Verification Ensures The Perseverance Rover Lands Safely On Mars
By Joseph Hupcey III - 28 Apr, 2022 - Comments: 0

By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by boulders, ditches, and tall cliffs — land formations that aren’t very welcoming to vehicles. Such was the case with the Mars Perseverance Rover's Landing Site: Jezero Crater. It’s not an e... » read more

Early Detection Of Reset Domain Crossing Errors
By Joe Mallett - 13 May, 2021 - Comments: 0

Many aspects of system-on-chip (SoC) designs are growing, including the numbers of gates, memories, clock domains, reset domains, power domains, on-chip buses, and external interfaces. A recent blog post focused on reset domain crossings (RDCs) and the requirements for effective pre-silicon verification of these trouble-prone structures. If properly applied, a solution meeting these requirement... » read more

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