tag: RDC

Techniques To Identify Reset Metastability Due To Soft Resets
By Siemens EDA - 05 Jun, 2024 - Comments: 0

Modern SoCs are equipped with complex reset architectures to meet the requirements of high-speed interfaces with increased functionality. These complex reset architectures with multiple reset domains, ensure functional recovery from hardware failures and unexpected electronic faults. But the transmission of data across sequential elements that are reset by different asynchronous and soft reset ... » read more

Reset Domain Crossing Verification
By Reetika - 13 May, 2024 - Comments: 0

By Reetika and Sulabh Kumar Khare To meet low-power and high-performance requirements, system on chip (SoC) designs are equipped with several asynchronous and soft reset signals. These reset signals help to safeguard software and hardware functional safety as they can be asserted to speedily recover the system onboard to an initial state and clear any pending errors or events. By definiti... » read more

Formal Verification Ensures The Perseverance Rover Lands Safely On Mars
By Joseph Hupcey III - 28 Apr, 2022 - Comments: 0

By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by boulders, ditches, and tall cliffs — land formations that aren’t very welcoming to vehicles. Such was the case with the Mars Perseverance Rover's Landing Site: Jezero Crater. It’s not an e... » read more

Early Detection Of Reset Domain Crossing Errors
By Joe Mallett - 13 May, 2021 - Comments: 0

Many aspects of system-on-chip (SoC) designs are growing, including the numbers of gates, memories, clock domains, reset domains, power domains, on-chip buses, and external interfaces. A recent blog post focused on reset domain crossings (RDCs) and the requirements for effective pre-silicon verification of these trouble-prone structures. If properly applied, a solution meeting these requirement... » read more

Designing Secure and Trusted Silicon Using Shift-Left in Verification
By Synopsys - 12 May, 2021 - Comments: 0

Designing secure silicon requires the design to be stable at all times, it shouldn't enter unknown states at any time to make it vulnerable from the security point of view. This paper identifies different sources of instability such as combinational feedback loop, unguarded clock and reset crossing, unguarded power crossing, etc. These instabilities can lead to unknown value propagation and hig... » read more

Requirements For Exhaustive SoC Reset Domain Crossing Checks
By Joe Mallett - 13 Apr, 2021 - Comments: 0

It is common to read that the numbers of clock domains and power domains in system-on-chip (SoC) designs are increasing, but for some reason there is less discussion about resets. There is no doubt that the number of reset domains is also rising; studies have shown that the single reset of twenty years ago has been replaced by a complex network of 40-50 domains in many chips and even 150 in som... » read more

Four Steps To Resolving Reset Domain Crossing Data-Corruption In Automotive SoCs
By Kurt Takara - 04 Feb, 2021 - Comments: 0

By Kurt Takara (Siemens EDA), Ankush Sethi (NXP), and Aniruddha Gupta (NXP) Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. Conventional clock domain crossing (CDC) veri... » read more

Systematic Methodology To Solve Reset Challenges In Automotive SoCs
By Mentor, a Siemens Business - 02 Dec, 2020 - Comments: 0

Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we prese... » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Shift Left Power-Aware Static Verification
By Himanshu Bhatt - 10 Oct, 2019 - Comments: 0

Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

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