Top Stories

Huge Challenges With Billions Of Things – Communication is poised in the next couple of years to cross a line between humans and things—things talking directly to other things as well as to people—setting in motion a series of technological, social and legal issues that will take years or decades to resolve.

The Problem With EDA Standards – In the EDA industry, does standard mean the same as it does in most industries? The Free Dictionary defines it as: Something, such as a practice or a product, that is widely recognized or employed, especially because of its excellence. In the EDA industry, a standards body is the place where EDA companies and customers come together to try and bring about convergence, often in a new or emerging area.

Paving The Way To 16/14nm – The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density.

Atoms, ARMs, ARCs, Andes…And All The Rest – There was a time when nobody believed Intel processors would be replaced with any other device. Intel commanded the processor market. This was not always the case. In the early days of the PC there were many contenders and most people thought that Motorola would win because they had more money behind them. Ultimately, Intel had the better, more scalable solution and it became dominant. Then along came a small IP company from England.

Experts At The Table: What’s Missing In The Internet Of Things – First of three parts: Understanding the usefulness of data, what to keep and for how long; focusing on solutions rather than just chips; networking issues caused by a flood of data; unexpected uses for data and technology; economic considerations.

Sensory Overload – There are two new buzzwords—always on and context-aware—that have the potential to transform devices and the way in which we use them. Both are related to smartphones at the moment, but this just the initial place where their impact is being felt.

Video

Tech Talk: 16nm-14nm Effects And Challenges – Electromigration, electrostatic discharge and thermal effects are all concerns at new process nodes. Here’s a look at what’s next.

Blogs

Everything Low Power: Low-Power Crisis = Danger & Opportunity – If you’re a student of these things, you’ve no doubt heard that in Japanese, the word “crisis” is divided equally into “danger” and opportunity.”

IP And LP In SoCs: FinFET Impacts For Reducing Physical IP Power Consumption – FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and process‐induced variability below 32-nanometer. FinFET technology is now in volume production.

Power Source: Current Generation Of FPGAs Pose New Power And Reliability Challenges – High-performance and low-power FPGAs require full custom design methodology, as well as power analysis tools for integration, modeling, power estimation and reliability.

Power Architect: ARM Cortex-A53, UPF & FD-SOI – New standards and new materials are going a long way toward improving performance and reducing power-related issues.

The Early Edition: What Do Timing Constraints Have To Do With Clock Domain Crossing? – As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical.

Whitepapers

The Internet Of Things Business Index – The Internet of Things (IoT) is an idea whose time has finally come. Falling technology costs, developments in complementary fields like mobile and cloud, together with support from governments have all contributed to the dawning of an IoT “quiet revolution”. Now, after more than a decade of slow progress, the business community is beginning to look seriously at the IoT.

CDC Verification Of Billion-Gate SoCs – Driven by growing design sizes and complexities and aggressive power requirements, design and verification engineers are witnessing an explosion in the number of asynchronous clocks. Consequently, design and verification teams spend a huge amount of time verifying the correctness of asynchronous boundaries on the chip. The paper describes three methodologies to address this issue and the benefits of each.

Property Synthesis Throughout The Design Flow For Application In Formal Verification, Simulation, And Emulation – A look at the problems encountered by property synthesis tool users and some proposed solutions throughout the design flow.

Power And Noise Integrity For Analog/Mixed Signal Designs – The convergence of advance process technology, increasing levels of integration, and higher operating frequencies pose considerable challenge to IP designers whose circuits are required to function in variety of conditions. However, it is becoming increasingly apparent that traditional and existing methods of considering power supply variation and noise are grossly inadequate.

Analog IP Migration Using Design Knowledge Extraction – Techniques for automatic circuit resizing between different technologies based upon knowledge extraction, which renders it very fast compared to full optimization approaches.

Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications – A study by the Linley Group of the No. 2 processor IP by volume and why the number of shipments is growing each year. The opinions and analysis are those of the authors.