CDC Verification Of Billion-Gate SoCs

Bigger designs and aggressive power requirements has led to an explosion in the number of asynchronous clocks. Here are some solutions.

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Driven by growing design sizes and complexities and aggressive power requirements, design and verification engineers are witnessing an explosion in the number of asynchronous clocks. Consequently, design and verification teams spend a huge amount of time verifying the correctness of asynchronous boundaries on the chip. The paper describes three methodologies to address this issue and the benefits of each.

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