Current Generation Of FPGAs Pose New Power And Reliability Challenges

High-performance and low-power FPGAs require full custom design methodology, as well as power analysis tools for integration, modeling, power estimation and reliability.


Today’s FPGAs are being used in a wide variety of applications such as consumer electronics, computer and storage, automotive electronics, and mission critical applications. The flexibility to configure the device based on its need, the ability to reprogram its functions, and the hardware parallelism it offers to quickly process very large amounts of data are some of the reasons why off-the-shelf FPGAs are becoming an attractive solution for its customers. With the markets’ continuous demand for higher performance and lower power products, the FPGA vendors need to steer their roadmap to achieve this objective.

Unlike ASICs, FPGA power consumption is highly design dependent because it is dictated by the utilization of logic resources, dedicated hardware and its routing to achieve the desired functionality. Today, the I/O performance metric is not only dependent on the sample data rate (Gb/sec) but also on power consumption per unit data (mW/Gb). Because FPGAs typically are used in high data processing applications, the FPGA vendors are constantly innovating through process technology, lower supply voltages, greater IP integration and various circuit design techniques to reduce power. But these advancements in high performance FPGAs impose significant challenges for power analysis solutions and methodologies.

The current generation of FPGAs use dedicated hardware resources such as I/Os, memories and other hard IP components to perform compute intensive operations. The use of dedicated hardware (IP) leads to significant power reductions as opposed to using large amount of logic resources to achieve the same functionality. These IPs can have different modes of operation with different power profile. Because FPGA power consumption is highly design dependent, one of the challenges for estimating the overall power consumption is to be able to accurately model each IPs’ power profile for different modes of its operation. Unlike standard cells, IPs cannot rely on .libs to provide data for power estimation and are totally dependent on the transient characteristics of the operating mode. Hence, there is a need for power estimation tool to handle multi-state IP power models, along with .libs for structured custom and standard cells, and characterize power for a full custom design.

Figure 1: Xilinx’s fourth generation ASMBL Architecture (Courtesy: Xilinx)

Another challenge in FPGA design is IP validation and modeling. It is important to validate the IPs standalone, but it is equally important to analyze the impact of the full-chip on the IP, as well as the impact of IP integration at the full-chip level. It is essential to perform transient power analysis of the IP and model its transient characteristics at the full-chip level, as the switching characteristics of the IPs will have a bearing on the robustness of the top level power grid. In addition, the switching scenario at the full-chip level will help expose design weaknesses within the IP blocks. The large scale of IP integration in FPGAs not only mandates accuracy but also underscores the need for handling capacity requirements at the full-chip level.

Circuit techniques such as power gating help reduce leakage power by enabling different blocks in the design to turn on or off based on the application. For FPGAs, power supply banks are used to turn off memories or I/O blocks when not in operation. These power-gated blocks need to wake up (power-up) in a reasonable amount of time without drawing excessive current from the power grid. Drawing excessive current can cause large voltage drop on the “always on” neighboring blocks. Consequently, some key design tradeoffs need to be considered when utilizing low-power circuit techniques such as leakage reduction versus on-state IR drop, determined by the number of switches in a design, as well as wake-up time of the block versus peak rush current.

The advancements in low-power process technology has been instrumental for total power reduction in current generation FPGAs. Technology migration as governed by Moore’s Law helps in achieving higher device densities, packing more functionality and performance in the same die area. However, increased current density, lower supply voltages and higher device threshold voltages lead to reduced noise margins, making power integrity analysis an important criteria for ensuring that required power is reliably delivered to all the devices. Owing to the high current and multiple power and ground domains that are typically employed in FPGAs, reliability issues such as time based failures and event based failures are key challenges that need to be addressed.

The emergence of 3D-IC technology is another innovation in the area of power reduction and performance. Multiple dies, either homogeneous or heterogeneous, can be integrated on the same silicon interposer to achieve the next generation performance using the current generation process technology. Additionally, 3D-IC technology offers significant I/O power reduction over monolithic FPGAs because the I/O signals are driven on chip through the silicon interposer rather than off chip through the IC package. As these factors make 3D-ICs increasingly popular, power analysis tools need to evolve to support such designs for its thermal and power integrity.

Figure 2: Xilinx’s stacked silicon technology uses passive silicon-based interposers, microbumps and TSVs. (Courtesy: Stacked & Loaded: Xilinx SSI, 28-Gbps I/O Yield Amazing FPGAs, Xcell Journal, Xilinx, Inc. )

As highlighted in this blog, high-performance and low-power FPGAs require full custom design methodology, which is driving the critical need for power analysis tools that can address IP integration, modeling, power estimation, and reliability concerns.

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