ARM Cortex-A53, UPF & FD-SOI

New standards and new materials are going a long way toward improving performance and reducing power-related issues.


The IEEE Standards Association Symposium on Electronic Design Automation (EDA) Interoperability was held on Oct. 24. I found the first session, Interoperability Challenges: Power Management in Silicon, with presentations by Erich Marschner of Mentor Graphics and Stuart Riches and Adnan Khan (both from ARM) to be particularly interesting. Earlier this year, the IEEE announced a new version of UPF with better capabilities for describing power intent and with broad support from the EDA industry. Last year ARM talked about its big.LITTLE strategy and its new Cortex-A53 and A-57 64-bit architectures. This year saw both of these advancements coming together.

Stuart Riches presented the slide below and emphasized ARM’s need to incorporate power intent constraints along with its IP and the need for this information to also be configurable. The IP Configuration phase of UPF in a design is referred to as “Golden,” the IP Creation piece delivered by the IP provider is referred to as “Platinum,” and the IP Implementation as “Silicon.” Figure 1 below from Riches’ presentation illustrates how this process works. Anyone working with IP and the newer version of UPF will likely see this terminology quite frequently.

Figure 1. Successive Refinement Process

What I found to be significant in the talk is that ARM is now shipping Cortex-A53 IP with UPF “Platinum” constraint files. This speaks to the usefulness of the new standard and the important role that it’s going to play moving forward in the industry.

ARM Techcon was held last week, and tying in with this month’s blog theme, David Jacquet, ST gave a presentation titled, “Energy efficient implementation of ARM® Cortex™-A57/-A53 processor cores in FD-SOI process technology.” He described how ST implemented a Cortex-A53 processor in ST’s 28nm FD-SOI process. There’s a good online copy of a presentation by Philippe Flatresse, ST on their FD-SOI process as well as a YouTube video overview.

The process looks quite fascinating. FD-SOI was mentioned in a previous blog comparing transistor technology where the issue of threshold voltage control for SoCs was brought up, and September’s blog also mentions IBM’s use of SOI for its Power8 implementation. One aspect that is unique to this technology is its ability to make use of body-biasing to control the power and performance of the transistors.

Figure 2. Vt Control Using Vbb (Buld, FD-SOI, FinFET)

Figure 2 illustrates the control over the threshold voltage that is available with the UTBB FD-SOI process that ST is using, especially in comparison to bulk or FinFET. Using a technique that ST calls “well-flipping,” it is able to further tailor transistors on the chip for better power and/or performance, as is shown below in Figure 3.

Figure 3. Process Selectable Wells for Multi-Vt Co-Integration

Jacquet claimed that for an ARM Cortex-A9 design and a forward body-bias (FBB) of 1.0V they were able to run at 300MHz @ 0.5V, 2.3GHz @ 1.0V and 3.0GHz @ 1.34V. That’s a pretty impressive range of voltages and clock frequencies. It also turns out that UPF is quite useful for FD-SOI designs too. He mentioned that the “Corrupt on Activity” (COA) feature in UPF was used to verify the Cortex-A53 design by covering parts of the design where the body-bias was used to greatly reduce power to the point where activity wasn’t permitted. In this case, using COA allowed simulation to detect and corrupt values on any activity when the design was operating in this low-power mode.