Top Stories
New Challenges Emerge With FinFETs – Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult. Here’s a look at what to expect.
Thermally Challenged – Chips run hot and the thermal densities increase with every reduction in fabrication geometry. What can be done about it?
Seven Ways To Improve PPA Before Moving To FinFETs – Henry Ford wrote in his autobiography, “Any customer can have a car painted any color that he wants so long as it is black.” And for decades, the semiconductor industry has marched to a similar theme set by Moore’s Law. But with the transition to finFETs harder than it first appeared, questions are beginning to pop up that are fueling a new round of confusion.
Powerful Software Optimization – It is commonly accepted that the higher you go in the design chain, the bigger the impact that design and implementation decision can have. While power optimization may have started deep in the silicon, the success of a product, such a smart phone, often is based on the time between charges. How do you extend that time?
What’s Next For Power Optimization – Today it is difficult to find a design that does not consider some kind of power optimization. Mobile needs it to preserve battery life, data centers need it to reduce operating cost, and many are finding they need it to meet tougher regulatory requirements. Where will future savings come from?
Blogs
Editor’s Note: It’s Time To Talk… – Ed Sperling writes that communication needs to improve inside companies, between companies and across disciplines to tackle future technology challenges. But even engineers don’t know what to call themselves these days.
Power Aware A-Z: 3D-IC Requires Expanded Power Grid Analysis – Mentor Graphics’ Christen Decoin contends that for advanced nodes, effective power grid analysis is critical to ensure interconnects can handle current demands.
IP And LP In SoC: Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics – Synopsys’ David Hsu writes that native low power simulation is inherent in today’s advanced simulation environments to understand power design intent.
Power Source: How Reliable Are Interconnects In 16nm FinFET Designs? – ANSYS-Apache’s Arvind Shanmugavel warns that designers need to pay close attention to interconnect reliability metrics for electromigration…or else.
The Early Edition: Door Busters In Low Power Optimization – Atrenta’s Mark Baker says big power savings are available with SoC-level power exploration…and he’s not alone.
Power Down: Power Optimization Considered – Calypto’s Abhishek Ranjan says there are big savings, but it’s important to know which power metric is being targeted for effective optimization.
Power Architect: Fastest Computers On The Planet – Nvidia’s Barry Pangrle shines a spotlight on The Green500 and the charge toward exascale computing. They’re faster, but much more energy-efficient than in the past.
