How Reliable Are Interconnects In 16nm FinFET Designs?

Designers need to pay close attention to interconnect reliability metrics for electromigration.


The 16nm FinFET process node is rapidly becoming the preferred choice for advanced Integrated Circuit (IC) designs. The 16nm node’s lower standby leakage characteristics and increased drive strength capability enable IC designers to push the boundaries of low power – high performance designs. However, the choice of the node is also accompanied by reduced reliability margins, requiring designers to pay special attention to interconnect reliability metrics for electromigration (EM).

Design for Reliability
EM analysis in advanced process nodes is no longer a mere ‘good-to-have’ check, but recognized as a rigorous ‘sign-off’ requirement. The 16nm node is no exception to this trend and IC designers have established clear methodologies and metrics for EM sign-off. Current SoC designs involve complex integration of digital logic, analog IPs, memory/custom digital blocks and high speed IOs. The reliability verification requirements differ significantly from full-chip SoC analysis to the different SoC components as detailed below.

SoC Sign-off Requirements
SoC sign-off for power grid EM requires careful planning from an early design stage. Typically, power grid architecture planning is done with only IR drop as the target metric. However, in the 16nm node, the grid architecture needs careful planning of metal widths and via types to avoid EM bottlenecks. Early prototyping and analysis to simulate the EM failures can avoid schedule slips during the final sign-off stage.

Application-aware EM analysis is a new approach that IC designers are using for reliability sign-off. Typically, power EM analysis is performed using an average toggle activity for all instances in the design. Using the average toggle activity for sign-off usually leads to over-design or under-design, depending on the end application of the IC. Historically, IC designers used a benchmark vector such as ‘Dhrystone’ to account for the average toggle activity across the chip. However, this benchmark could prove to be optimistic or pessimistic depending on the mode in which the IC operates during its lifetime.

During the operating lifetime of an IC, it can cycle through multiple modes with a specific amount of time in each mode. For example, an application processor in a smart phone can transition between modes such as audio/video playback, call answer, GPS usage, browsing/social media and an idle mode. Each of these modes has a typical percentage usage during the lifetime of the IC. Industry studies show that the idle mode — where only certain baseline functions are enabled in the background — typically accounts for more than 90% of the IC’s lifetime, whereas the browsing/social media application usage accounts for less than 3% of the lifetime. Using a lifetime-averaged toggle activity based on the vectors for different modes can lead to a more realistic EM analysis. It is clear from the above example that the end application of the IC along with the lifetime usage could drastically alter the way in which EM sign-off is performed. With the reduced EM margins in the 16nm node, IC designers are increasingly using more realistic application-aware EM sign-off.

With increased interconnect resistances and high switching device currents, self-heat checks for signal nets are major sources of concern. Self-heat EM checks, including the RMS signal EM analysis, are mandatory for sign-off at the SoC level in the 16nm node.

Thermal characteristics in the 16nm FinFET process are typically worse due to tightly packed fins and poor heat escape pathways. Using the worst-case temperature could lead to pessimistic EM results due to the exponential dependence of temperature on EM limits. Thermal aware EM analysis can be used to reclaim the margins lost due to worst-case temperature usage. Using accurate spatial thermal distribution of the die for EM analysis can significantly decrease the number of false EM violations during sign-off.

Library Requirements
Reliability verification for standard-cells in the 16nm node has its own set of challenges. There is an abundant usage of local interconnects at the standard-cell level in smaller technology nodes. These local interconnects have a significantly lower EM limit than the upper metal layers. A transistor-level power and signal EM analysis needs to be performed on the libraries to ensure that standard-cells can operate reliably over the lifetime of the IC. EM sign-off needs to be performed with a range of output loading conditions and operating frequencies. This will ensure that the standard-cells can operate across a range of frequency-load conditions without EM failures. To obtain the proper coverage on all signals and power nets inside standard-cells, a vectorless approach that exercises all nets needs to be employed. Accurate transient signal switching behavior needs to be simulated to capture the true EM violations inside standard-cells.

Analog and Mixed-Signal IP Requirements
Analog and mixed signal IPs are either designed in-house by the IC design teams or obtained from a third-party IP provider. The current consumption for any analog or mixed-signal IP depends on the vector used during simulation. Electromigration for both power and signal needs to be verified using the appropriate vector set. All the necessary devices and nets need to be exercised to make sure proper coverage is obtained during EM verification. Analog IPs tend to have complex layout structures for proper matching of resistances and currents. In the 16nm node long metal interconnects tend to have significantly lower EM limits than shorter wires. To alleviate this problem, it is typical to use layout techniques with shorter metal routes inside analog blocks.

Custom digital IPs, or compiler memories such as SRAMs, RFs and CAMs, have other sets of challenges for EM verification in the 16nm node. Power and signal EM needs to be verified using an exhaustive vector set to toggle all the nets in the design. When obtaining an exhaustive vector set is not possible, vectorless analysis with proper toggle rates for different nets should be used for sign-off.

IP validation for EM is a two-step process. The IP not only needs to be validated for EM as a stand-alone block, but also within the context of the full-chip using appropriate models. Analysis accuracy and modeling accuracy are both important for IP EM sign-off.

With the onset of designs implemented in the 16nm FinFET process node, EM sign-off is no longer a “good to have” but a “must have” requirement. Design for Reliability needs to be an integral part of today’s design methodology to ensure quality power and signal EM sign-off from standard cell library to analog and mixed-signal IP, and all the way to the full-chip SoC.

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